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Comment by Noone10101 | Hacker News Reader

This article is just an advert. I have worked on practically the same project as the second example with a different manufacturer and can tell you it is a lot more expensive than 5 million. This project was 90nm,3 years ago so comparable to 55nm nowadays, and minus the mcu, so there is no licensing costs. NRE of 20 million for design, development, and bringing to production. And I think it ran over budget, with only 1 silicon revision. With a final component cost of $1.20, it finishes up cheap compared to the cost of individual components, but the up-front costs are much larger than they are suggesting. They only list mask sets here, not mentioning engineering time for 12+ months and design license tools, costing upwards of 1 million per seat. Then on top of that the PDK from the manufacturer. I would love to see the full cost breakdown and see where it becomes viable.

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I work at a company that does these sorts of custom ASICs for a variety of customers all the time. $5M for the second example is a bit low but the right ballpark. Even allowing for 2 mask sets (mistakes happen) and $1-2M for an off the shelf bluetooth IP it would be difficult to see this going much over that.

I'd estimate a team size peaking at < 10 over 12 months to go from initial specification discussion to GDS-II. Another $1-1.5M for qual and support through production plus silicon validation.

Put that all together and <$7M sounds to me like a good estimate and I've seen a lot of more complex projects come back for less.

Not wanting to be a gobshite here but how did you manage to spend >$20M for something like this? It sounds like you were being seriously ripped off if you were paying $1M per engineer for design tools - you might want to push your tool vendors on that next time negotiations come round.

The second example is a medical IoT telemetry device. If the parent’s project had antenna in package I totally believe $20M for the project, especially as it includes rf validation, the bringing it to market part. $1M per engineer is a lot, especially for typical VLSI cad stuff, but possible for some “design” tools. I’ve used some specialized field solvers that cost $500k per engineer. Not sure that AiP in 2017 would’ve required that, but maybe.

I agree, there probably were some wastage on our project, but I'm only a lowly engineer so cannot really comment on high level decisions. There were a lot of engineers working on the project, wages tends to drive prices up quickly, and all the ip was developed from scratch. I don't work there anymore, moved to a smaller more nimble outfit. Thanks for your insight

An anecdote, the Allwinner, the company that once made MP3 and MP4 player chips made once thunderously popular A10 SoC with just $1,000,000 USD (set as a condition of the investor.)

Though, I admit, making just any IC under $1m requires really knowing what you are doing. Not something for a team of green engineers, and engineers whose only experience was doing cookie cutter SoCs from hard macros.

Well, if you steal all the CAD tools, design is pretty cheap ...

EDA CAD tools are infuriatingly expensive. You can get a chip run on an older node (180nm or 250nm) for <$100K. Good luck finding a set of EDA CAD tools for under that per year.

I used xcircuit, magic and irsim in university to make plenty of ASICs at MOSIS. Many universities still do. One can even get the NCSU PDKs for MOSIS for free. Totally compatible with 0.18u http://opencircuitdesign.com/magic/

Magic is sorta okay as long as you stick to low-performance digital or very small analog transistor counts.

The problem is that most of the "interesting" circuits for old tech nodes have a significant analog piece or RF piece--generally either ultra-low power(nanoamps) or higher voltages(15V+) or higher frequencies (2GHz+).

Both the simulation models as well as the tools to extract parasitics are extremely weak (or non-existent) on the open source front for analog and RF circuitry.

Does this apply to the formerly commercial Bravo3VLSI from the 80ies, now available for free & open-sourced as Electric from https://www.staticfreesoft.com too?

Yes, unfortunately.

Anything based around Magic has to run on an extremely simplified set of rules in order so that the tiling and stitching mechanisms that it uses don't get upset.

DRC and extraction are hard. They require line-sweep geometry engines of fairly significant sophistication. Extraction requires some notion of third dimension matching and/or analysis.

The problem is that Cadence will donate tools to practically any school but will take your firstborn if you're a company--and Cadence are one of the better companies in the EDA space. This cuts off any incentive for someone in academia to create a new VLSI tool.

Note the accepted papers at DAC 2020: https://www.dac.com/content/2020-dac-accepted-papers

Not a single mention of "DRC", "rule", or "extract." Even simulators are thin on the ground unless you include "quantum". You would think that extraction, DRC, RF simulation, etc. are all solved tasks, right? (I assure you that algorithms in these spaces that can exploit massive parallelism are quite rare and are very difficult to implement well) :(

We should be living in the time of massive GPU and cloud acceleration of these tasks, and yet ... nothing.

This tells you what research is getting funded.

(Edit: Sorry, Largo, for some reason your down comment isn't getting a reply button...)

Edit: Magic, in this context, refers to the VLSI layout tool. Most open source EDA systems default to Magic as the thing that you use to draw/interpret physical geometry. This is good code reuse, but bad in that you inherit all of its limitations.

Thanks for the fast response. What do you mean by magic in this context, are you referring to the program mentioned by the GP, or 'magically' simplifying DRC etc. as offered by Electric?

edit: I wasn't even aware of https://www.dac.com/ -> one more fractal in the Tsundoku stack

edit: never mind :-)

The basic point that older nodes are still viable and exponentially cheaper than newer ones (and getting cheaper over time) seems very much correct. It's not just the physical masks either; the design rules get simpler and more openly available the further back you go, and entirely open toolchains with negligible licensing costs start becoming viable as well. In fact, this might end up being the 'real' Moore's law, not so much the availability of more and more advanced nodes at the leading edge.

Are there any resources I could read or watch to understand why it's so expensive to produce mask sets vs compiling code for an FPGA?

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