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Comment by kllrnohj | Hacker News Reader

> What does that mean? Advertise to whom?

Runtime detection is the process querying what extensions are available, and then selectively using those. You adjust what the query returns to only return the common set.

Runtime detection has been a pretty standard thing for well over a decade now - it's how we all manage to run the same compiled binaries over the years despite variability in SSE & AVX support. You don't download different versions of Chrome/Photoshop/Gimp/Premiere/Blender/Whatever compiled for different CPU micro-architectures, do you? You might if you run Gentoo I suppose, but that'd be about it.

> Does it mean that I can’t compile with -mavx2 anymore?

You already can't if you're shipping binaries to users unless you only support Skylake & newer? There's a lot of CPUs currently in use that don't support AVX2. So... you either already have this problem and you're familiar with it, or you're not doing this and it's moot.

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Runtime detection is the process querying what extensions are available, and then selectively using those. You adjust what the query returns to only return the common set.

Except that they almost always do this runtime detection once, on startup, and then choose/thunk codepaths accordingly. If the OS just happens to start my avx2 process on a little core (and how is it going to know better?), that's going to turn off all of my optimizations, regardless of where the process subsequently gets migrated to.

Except nobody in 30 years of x86 dev expects to get a different answer from CPUID during runtime.

.. and within a function because the scheduler decided to move you to a different core.

If all the cores are configured to advertise the lowest common denominator instructions it will work.

But that defeats the purpose of supporting any extensions at all in the big core that the little core doesn't support. Software will get the lowest common denominator answer and just not use avx2. So why support it in the first place? Why not just do the right thing and have uniform extension support like big.LITTLE?

Chips aren't designed from scratch. They're assembled out of previously designed components and in this case Core cores and Atom cores were never designed to work together.

No - but that just means that Intel shouldn’t do this at all. Either don’t support stuff like avx and avx2 in the big core by disconnecting those blocks or support a slow microcode version of avx and avx2 in the little cores. Supporting different extensions for a CPU used with modern preempting OS’s doesn’t make any sense.

> Either don’t support stuff like avx and avx2 in the big core by disconnecting those blocks

That's partly what they did. From the article: "One thing we can confirm in advance – the Sunny Cove does not appear to be AVX-512 enabled."

Maybe they also fused off AVX & AVX2 support in the Sunny Cove core as well, we'll see.

And disabling AVX in cores that otherwise support it is already a common thing - see the Pentium & Celeron lineups that Intel currently sells. They don't have AVX/AVX2, even though the cores inside them definitely could offer it.

Currently Intel likes to disable features on some models of Core cores for product segmentation reasons. I'm pretty sure processors sold under the Pentium or Celeron brands already have enough features fused off that they're roughly comparable to the Atoms this is being pared with. You also fuse off things like sections of cache or whole cores that have manufacturing defects.

The typical x86 extension query (cpuid) is an unpriviliged user-mode instruction — unless the application takes care to ask the OS, there's no real way for the OS to select the common denominator.

Edit: Also: AVX2 is a lot older than Skylake. You're probably thinking of AVX512.

The OS could still intercept CPUID - this is, after all, what VMs do.

But it looks like Intel is doing this anyway, as Sunny Cove in this application has had its AVX-512 removed anyway: "One thing we can confirm in advance – the Sunny Cove does not appear to be AVX-512 enabled."

Well then you need to set up a VMM for the OS…

Running every thread in a hypervisor just to trap cpuid sounds like extreme overkill. And probably some applications want the features only available on the big core, and masking those out doesn't solve that end of the problem.

> You adjust what the query returns to only return the common set.

But this shoots the big core in the foot. You run at the lowest common denominator and the big core doesn't have the advantage of higher clocks. And this might just lead to a lot of software that only runs on the big core.

Imagine you wanted to fly around between multiple points but if you want the option to ever switch to a bus then your plane will circle around each airport until it's as slow as the bus. Or you can opt for "plane only".

It only shoots the big core in the foot for things that would make meaningful use of the extensions present on the big cores but not on the little ones. Which in a 7w application is what, exactly?

Anything that uses any AVX or FMA3 off the top of my head.

A better mix would have been simply using lower clocked, lower powered cores of the same type or really close derivatives of the big core where the manufacturing process and clocks are what keep power low. Not a mix of Ice Lake and Atom. But right now Intel would throw everything at the wall to see what sticks.

And it seems like a good way for developers to make sure their software stays on the big core.

memcpy?

The fact that they put the extensions in implies they expect meaningful use, doesn't it? If not on this specific part, on a future part with multiple big cores.

Meaningful use in a particular market != meaningful use in all markets.

AVX2/AVX-512 is great in HPC workloads, for example. But nobody is running an HPC workload on a 7w netbook, now are they?

What is useful on Xeon and what is useful on Atom are different. This is an Atom-class SoC used in Atom-class applications, not a Xeon-class one.

That doesn't address what I said at all. This is about extensions that are in this Atom-class SoC.

>> Does it mean that I can’t compile with -mavx2 anymore?

> You already can't if you're shipping binaries to users unless you only support Skylake & newer?

Huh? My 6+ years old gaming PC supports AVX2, and it definitely doesn't have a "Skylake & newer" CPU!

AVX2 support started at Haswell, or Intel core 3rd generation. We're at gen 10 now.

While there certainly are still a lot of systems without AVX2 support, new games (and other performance hungry software) requiring it would not be completely unreasonable.

Intel is still launching new processors with AVX2 disabled. They use AVX2 support for product segmentation and disable it on low-end parts. So a Comet Lake Pentium Gold CPU launched in Q2 2020 doesn't support AVX2.

(I recall a recent news story about how unawareness of this among people writing or documenting compilers has started to cause problems.)

Using IA for market segmentation purposes is such a classic from the "Bad Intel Ideas" basket...

That's very surprising, disappointing and extremely short-sighted from Intel.

> (I recall a recent news story about how unawareness of this among people writing or documenting compilers has started to cause problems.)

You can't blame them!

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