I've actually played with that idea as well in the past, as a mechanism for emulating other architectures. Who wouldn't love a RISCV that you can turn into a passable x86 or M68K or whatever? In the past too, there were user programmable uCode machines intended to be a generic platform for pretty arbitrary ISAs, so it's not an entirely crazy idea. I eventually came to the conclusion that programmable fabrics in the critical path like instruction decoders on modern processors didn't make sense from a timing perspective, and a classic RISC (or VLIW like Transmeta/Denver) + JIT continued to make more sense. In hindsight I believe you can see this in x86 cores where the microcode ROM is pretty much only executed in already slow paths, and the patch RAM is even more anemic. I'd imagine you'd hit the same issues.
That being said, my experiments were hardly conclusive and I'd absolutely love to be proven wrong.