Imec Demonstrates FinFET Devices with Integrated Tungsten Buried Power Rails
imec-int.com
imec-int.com
[1]
"There are limits to the scalability of the individual devices and as process technologies continued to shrink towards 20 nm, it became impossible to achieve the proper scaling of various device parameters. Those like the power supply voltage, which is the dominant factor in determining dynamic power were particularly affected. It was found that optimising for one variable such as performance resulted in unwanted compromises in other areas like power. It was therefore necessary to look at other more revolutionary options like a change in transistor structure from the traditional planar transistor."
"FinFET technology is being adopted in a variety of forms by IC manufacturers who need to increase the density of their ICs without using such small feature sizes that the device performance falls. As a result, FinFET transistor technology has enabled the development in IC technology to continue to follow Moore’s law."
Feature sizes: Possible to pass through the 20nm barrier previously thought as an end point.
Power: Much lower power consumption allows high integration levels. Early adopters reported 150% improvements.
Operating voltage: FinFETs operate at a lower voltage as a result of their lower threshold voltage.
Operating speed: Often in excess of 30% faster than the non-FinFET versions.
Static leakage current: Typically reduced by up to 90%
And for the "buried power rails":
[2]
"Buried power rails (BPRs) have recently emerged as an attractive structural scaling booster allowing a further reduction of standard cell height in highly scaled technologies. Power rails, which are part of the power delivery network, are traditionally implemented in the chip’s back-end-of-line (BEOL, i.e., the Mint and M1 layers). BPRs on the contrary are buried in the chip’s front-end-of-line (FEOL) to help free up routing resources for the interconnects. Moreover, they provide a lower resistive local distribution of the current to a technology that suffers from increasing BEOL resistance with pitch scaling. "
[1] https://www.electronics-notes.com/articles/electronic_compon... [2] https://www.eejournal.com/industry_news/imec-demonstrates-ex...
1. As nodes were getting smaller, and metal layers thinner, the power had to migrate lower, and lower in the backend, where they compete for space with signal traces, and add to cross talk problem
2. Smaller, and smaller power rails had bigger, and bigger leakage.
3. As more, and more exotic device geometries were appearing, the more limitations on how power delivered to them were appearing.
4. Voltages were getting lower, and lower, and copper losses, and demands on DC-DC regulators higher.
Buried rails attack 1) by simplifying cell design, and taking cross-talk out of the picture as such. Signal simply doesn't compete with power at all now; 2) By allowing buried rails be made as big as needed, and on top of that, they can be buried in High-K; 3) By making just any geometry in Z axis possible without power influencing its design; 4) By increasing conductor sizes, as said above, and allowing for placing regulators on the other side of the wafer using TSVs.
https://www.coventor.com/blog/3d-nand-challenges-beyond-96-l...