Most of that verification infrastructure is tied to proprietary tooling in some way or another. In the case of IBM they have a lot of in house EDA tooling that they aren't willing to release or even talk about much. They extended vhdl with "aspect oriented programming" to implement their approach to verification. Most of the other verification tooling for verilog (now system verilog) started as proprietary extensions by some vendor (Intel, Synopsis, ...) and then made it into the system verilog standard. None of those verification parts of system verilog have an open source compiler that supports them.

The good news is that at least the simulation part has improved massively over the last few years. For synthesizable system verilog you have https://www.veripool.org/wiki/verilator, which allows you to compile to C++ and then you can implement any verification methodology you like from scratch in C++ :). I did that for parts of an in-house POWER based processor and it isn't actually as bad as it sounds. You also have the option to use DPI-C and interface with a C++ test-driver that way. We managed to do extensive Hardware and Software (full hardware abstraction layer + instruction compiler + FPGA + ASIC) co-simulation for an accelerator we build, although using proprietary tools because we had Xilinx IP and VHDL involved. Verilator is also used as a backend for Chisel.

For vhdl there is https://github.com/ghdl/ghdl.