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jackyinger

TL, DR: You want a retimer since it doesn’t amplify noise and distortion like a redriver does.

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This article is from a company that sells... retimers.

At the cost of a bit more latency.

And money, and power.

A retimer is a much simpler device (thus cheaper) and can be tested using linear methods. To test a line with a redriver you really need a full on BERT system + a VNA whereas you can get by with just the VNA for the retimer. To accurately characterize PCIe Gen 4 and 5 you need to go to almost 50 GHz of bandwidth on your test equipment so you are talking big money on hardware for test, design, and validation.

Meanwhile, a redriver doubles your power budget on the driver since it literally is a second set of drivers in the middle of your PCIe line.

This is an ad from a company that sells redrivers. It's an informative ad, but still an add so it should be viewed with a critical eye.

Looks a retimer is much more complicated than a redriver.

From my experience any company that is developing interconnects either has the needed test equipment or uses a test house. It seems strange that access to test equipment should factor into an engineering decision.

The test equipment is hundreds of thousands of dollars each and everything used for PCIe3 doesn't have the bandwidth to go to PCIe 4. The bigger companies have no problem scaling up but for smaller players it's a serious consideration. Even at satellite offices of larger companies, it can be difficult to get the capital outlay for your lab to buy something like a BERT. We're talking millions of dollars at scale. Fortunately, most of the equipment that works for PCIe4 will also work for PCIe5.

I worked in a test house for seven years. The last thing I did before I left is automate PAM4 25GBaud transmitter and receiver testing. I am intimately familiar with the costs. I am also familiar with how necessary it is for every player to have access to this equipment.

And so if there is a need to increase bandwidth there could be an engineering decision to either go with faster links or more links at the existing speed. Faster links has the extra cost of involving more expensive test equipment, more links does not. Strictly speaking perhaps engineering decisions should not consider cost and that's one for the bean counters, but I don't think that's the reality for smaller teams where those two worlds merge.

Engineering decisions absolutely include cost. It's part of the classic triangle: Cheap, Fast, Good; pick two (or one).

Yes but if cost is dictating the quality spec then you aren’t accomplishing anything of value.

You're right that a design, verification and test bench can easily rack-up several hundred thousand dollars worth of equipment.

But there are trade-offs that can lower the capital cost, like leasing the equipment, using a third party for aspects of the design/test, carefully evolving known good designs and simply budgeting a lot more for more PCB re-spins.

In the finally analysis those to want to make products in this domain aren't doing it on a shoestring budget, it's going to cost a lot no matter what.

You have flipped the definitions of redriver and retimer.

Also, while I agree with big money for hardware, do you see a way around if your design needs a retimer?

You're right, I flipped the names in my head. I probably shouldn't be posting so late so I'm going to bed after this comment.

You can go a long ways with careful design and quality redrivers, but at some point it will be better to go to a retimer. Which you should use is a matter of use case and engineering decisions. Just please be skeptical of the conclusion that "Usage [of redrivers] is highly discouraged; use at own risk" from a company that specifically designs and sells retimers.

You're lucky to get latency under a microsecond on PCIe to begin with. A buffer of 20 bits would be about 2 nanoseconds and completely negligible.

Though apparently retimers are allowed to spend up to 64 nanoseconds? What takes so long? Especially when the PCIe spec casually asserts the existence of <10ns retimers.

I assume that's relevant for crossing clock domains or when using (distinct) spread-spectrum clocks.

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