Why is RISC-V even so hyped up/successful? Other open ISAs precede it, and AFAIK the code density that RISC-V allows is disappointing considering the designers had an opportunity to start from scratch.
There's various reasons for a new ISA. The most appealing right now is the patent pool. Most other open ISAs are explicitly patent encumbered (recent MIPS versions) or provide zero protection (openrisc). The chances of getting sued over RISCV seem very small until you start moving to non-ISA parts of the chip.
For an ISA to succeed, the ISA itself is a distant second to the ecosystem as x86 shows so well. The amount of money an R&D being poured into RISCV would single-handedly be enough reason to adopt.
Right now, x86 needs one set of instructions for each SIMD data size. That’s why we have SSE, AVX, AVX512, etc. This introduces complexity for both hardware designers and software designers. You have to actively update software to work with newer chips with larger SIMD registers. In the proposed RISCV design, you wouldn’t have to. It would just work on all sizes.
RISC-V will need to do the same, so expect to see multiple versions of the "V" extension over time.
If you look at the encodings, many of them are actually the same opcodes as the original MMX, but with prefixes.
In the proposed RISCV design, you wouldn’t have to. It would just work on all sizes.
That doesn't make sense --- how would the code know how much to increment pointers by, how many times to loop, alignment, etc. ? Unless they added some really un-RISC instructions to do automatic vectored operations (like if x86 had a REP ADDSB), I don't see how you wouldn't need to change software for changing SIMD widths.
You ask the hardware. The current vector width is a register that can be set and queried.
Configuring a grouping of 8 registers for a vector of 16 elements might look like overkill because 128 bit vector registers are sufficient and should be widely available. On the other hand, there might be a CPU with "V" support that just implements - say - 64 bit vector registers where we would need to group 2 registers. Since a grouping thus may be needed it really doesn't hurt to configure the maximum here.
...seems to imply that the generated code may still need to assume certain widths.
It's just that if your code doesn't need 32 different vector variables then you can step down to, say, 4 variables with 8x longer registers for more efficiency. You need to know how many live variables your code has (which the compiler knows), not how long the registers are.
The RISC-V ISA with the Compressed extension is very competitive and often better pretty much anything else.
RISC-V also has an innovative modular structure that allows it to be optimally used in many different industries while sharing a lot of code.
The RISC-V Vector extension is really good and innovative. And so are some of the other extension.
IIRC the code density beats ARMv8 and x86_64 in most situations.
Do you have any in mind? From what I can tell even POWER is not as open as RISC-V. They only show schematics to their partners, not the public at large.
POWER opened up only after RISC-V.
Relevant Wikipedia page: https://en.wikipedia.org/wiki/Comparison_of_instruction_set_...