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Comment by jmt_ | Hacker News Reader

Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics background so I'm struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?

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The number 7nm 5nm etc. ceased to refer anything physical after the technology moved on from planar transistors. Now it's just a commercial name for a generation.

The most important dimensions are the gate pitch and metal pitch. For TSMC's 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial name.

They are not even comparable across companies. For example, TSMC 7nm process technology has 91 MTr/mm², Intel's 10 nm prosess technology has 100 MTr/mm². Samsung 10nm has 52 MTr/mm². (MTr/mm² refers to millions of transistors per mm²).

That's interesting, I saw a hobbyist photo lithography setup the other year that was able to etch metal with a resolution of 20nm.

That's really not possible. 20um probably. Micro not nano.

Well, nano would be achievable via e-beam lithography, but photolithography is another beast: I'm pretty sure you need EUV at that size, with special (expensive) lenses that do not absorb the UV.

I recall this but don't remember seeing anything smaller being posted. Sub 100nm for a hobbiest would be pretty awesome. https://youtu.be/YAPt_DcWAvw

State of the art non EUV photo lithography uses light with a 193 nm wavelength. 20nm is significantly below that which would imply usage of highly advanced lithography techniques like multiple patterning. A chip manufactured with a 20nm resolution would involve dozens of masks which were created through electron-beam lithography. Just the mask set alone would cost millions of dollars.

The only hobbyist that I am aware of used a pretty nifty mask less technique but the resolution doesn't come close at all. I think you just mixed up your units.

Can't edit this, what I saw was definitely um and not nm.

What's the MTr/mm2 for TSMC 5nm? 2nm?

EDIT: looks like 173M for 5nm. https://en.m.wikipedia.org/wiki/5_nm_process

TSMC 5nm is 170 MTr/mm2. Then it's goes above 200 MTr/mm2

Intel 7nm is something like 200 MTr/mm2.

Any news on 2nm?

Very interesting, thank you. So we're basically not nearly as close to "true" 7nm as I thought? Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?

According to this video using an electron scanning microscope on amd and Intel chips, the “7nm” or “10nm” number does not measure anything, and is effectively a process version number for marketing. From memory there is no single number for measuring transistors or efficiency, transistor density is useful, but it doesn’t tell you the performance or power usage.

https://youtu.be/1kQUXpZpLXI

Both performance and power usage are physically functions of transistor density. Assuming the apples-to-apples comparison of similar transistor counts, operating TDPs, and processor designs.

Moore's law always was an economic roadmap. Everything in the semiconductor industry is (was) planned around the transistor density doubling every two years, from hardware investments, to market segmentation, to microarchitecture design, to software optimizations. So I think it makes sense that they go on with pushing transistor density from generation to generation, and convey it to the public using names it is already familiar with.

It's right that power has severely limited performance despite increasing the transistor density lately. Maybe we'll once again get better with adiabatic computing?

For whom? Surely the people ordering chips know the truth.

>Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?

If you will forgive the expression. Yes and No.

Yes in that TSMC has ideas / plans scaling all the way to 0.8nm, targeting 2030. That is only a few steps above what you described as true 7nm.

No in that no one knows if it will work. We know Quantum Tunnelling will hit some day, some where, some how, at some percentage.

Remember you are talking about leading edge Semi-Conductor manufacturing. Nothing like this has ever been done before.

It is a bit like telling me 5G today was possible when I was researching on first gen 3G two decades ago. If you describe to me with theory I will have properly said yes..... but it is hard to imagine how it will actually be implemented.

Technically it’s figured out. Gate-all-around has been experimentally demonstrated at pitches less than FinFET. The primary problem is, who is going to pay it. The economics are very tough at these 1s of nm nodes but hopefully that’s only a transitory problem.

You are talking about GAA at 2nm, I was talking about sub 1nm ( Node naming ) Tech. Which the OP was referring to "true" 7nm or Gate pitch / metal pitch at sub 7nm. We are still quite far away from figuring those out.

But yes, I agree the economics model is tough as I have been stating on various forums for years. That is part of the reason why we see Semi-conductors consolidation, like Marvell, Broadcom.

My best guess is that some time in 2026/ 28 we might have to stretch the cycle to three years instead of two. Giving more time to amortised those cost. But HyperScaler Cloud Market seems to be not limited by any R&D funding so I am actually quite optimistic we could see the current 2 year cadence all the way to 2030. Anything beyond is just too hard to predict or infer.

To make transistors smaller, and not just draw them with finer resolution, the industry will need a new way of controlling the channel. FinFET got us here. Most likely gate-all-around will be the technique that gets the “true” geometries smaller.

https://en.m.wikipedia.org/wiki/Multigate_device#GAAFET

For perspective, 2nm is approximately how much your fingernail grows in the time it took to read this sentence.

(3.47mm per month)/(30 * 24 * 60 * 60 seconds) = 1.33nm/second

That's a fun factoid to know. Thanks

der8auer recently did a 3 part video on YouTube where he cut up AMD and Intel chips and looked at the transistors with an electron microscope. It sheads some light on meaning (or non-meaning) of the node names. Is also really interesting;

https://youtu.be/uEMDkbF3hu0 https://youtu.be/uXu_1zXOZdY https://youtu.be/_wAeL3f3iV4

With all the electronics and physics chans I binge on youtube I'm surprised this one never hit the suggestion fan, it's utterly fascinating

der8auer is basically the patron saint of PC overclocking, highly recommend his coverage of new hardware because he goes straight to doing interesting stuff and skips the usual review stuff that everyone else repeats.

I think we left the holy land of pc overclocking long ago.. this dude just showed us chemical coating of transistors.. Even Applied Science would be jealous.

The nm process numbers refer to the necessary dimensions of a theoretical planar transistor to achieve the same density as this process. Planar transistors haven't been used for at least a decade. To make matters worse there is no standardized planar transistor design so ultimately you cannot derive any meaning from these numbers other than as a fancy version number that tells you which process is newer. As many others have commented: It's much better to just look at overall transistor density.

FinFET and GAA (gate all around) are 3d transistor designs. Therefore you get impossible and purely theoretical planar numbers.

It's easy. You take a very small number, add the letters 'nm' to it, and then start sending out press-releases to the major media outlets.

That number has nearly zero bearing on the actual physical sizes of the chip's components.

The only people who know about the exact dimensions are the firms placing manufacturing contracts with TSMC.

You get it

>That number has nearly zero bearing on the actual physical sizes of the chip's components.

AFAIK the reason behind this madness is that the number previously did correspond to feature size, but then they discovered methods of increasing transistor density without decreasing the size of the components. Since the feature size was used in marketing as a proxy for transistor density, they felt it was ultimately justified to decrease the number. After all, if your enhanced 32nm process provided the same transistor density as your competitor's 22nm process, why shouldn't you market your process as "22nm"?

That number used to set the scale for the design rule set.

https://www.electronics-tutorial.net/Digital-CMOS-Design/CMO...

Not the explanation you're looking for, but the CTO at TSMC co-invented the modern FinFET transistor. They've probably good a really good grasp on what issues block development of smaller features, and know how to find ways around those limits.

https://spectrum.ieee.org/semiconductors/devices/how-the-fat...

He also wrote an excellent introduction to semiconductor physics textbook, that Berkeley hosts for free!

https://www.chu.berkeley.edu/modern-semiconductor-devices-fo...

Thanks!

To make an analogy: I think a good way to think about it is that the 7nm node doesn't actually produce chips with 7nm features, it uses a "knife" (actually it's a lithography process) which is able to cut things as small as 7nm . That enables it to be more precise than a bigger "knife" so even though the size of the chip features is >7nm they are still able to be smaller than features cut with a 10nm "knife".

I don't actually know anything about chip production. But that's what I've picked up from HN.

One thing people are trying to convery every time this question comes up is that "7nm" is really just a marketing number, it's not tied to any particular physical dimension, and it's not how small the knife is able to cut.

The knife does get better, it's just not something that the Xnm node names measure directly.

That's kinda the idea. There are also several different layers each with its own resolution.

Also, well, that number isn't really the actual resolution of the finest layer, but is some "marketing processed" message that should give you an idea of the chips performance. It used to have the meaning you stated, but things changed a while ago.

der8auer "14nm and 7nm are NOT what you think it is - Visiting Tescan" https://www.youtube.com/watch?v=1kQUXpZpLXI

for reference "TESCAN is a leading global producer and supplier of scanning electron microscopes, focused ion beam scanning electron microscopes and micro-CT solutions."

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