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Even if you know which accesses have a high probability of missing in core or chip cache, it is tricky to write portable software that takes advantage of (switches/branches to other work) the time it takes between prefetch and data available in L1. It is not just architecture specific, or microarchitecture specific, it's chip specific.

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Not sure I understand your comment.

Many things may go wrong, interference from another hardware thread running on the same core, context switches, cache associativity shenanigans, and more.

But still, if you prefetch, switch a co-routine so that other one is spending their 100-500 CPU cycles doing something else, then switch back — I would expect statistically significant performance win, at the cost of code complexity.

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