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Comment by spamizbad | Hacker News Reader

Not sure if it's still the case but RISC-V was beating ARM in code size as well

I find that a bit surprising since my understanding is RISC-V is more minimal (has fewer higher level instructions) (ATM, that will change with extensions) then ARM.

This paper refutes your point and is inline with my understanding: https://carrv.github.io/2020/papers/CARRV2020_paper_12_Perot...

One counter point is the simpler the ISA the more work the compiler needs to do. So x86 is may be easier to write an optimize compiler for given it does some of the work for you (despite the bloat).

I wonder how much benchmarks on the current ARM and RISK-V chips will change over time due to compiler improvements. ARM probably already has alot of investment in some workloads...

EDIT: This presentation show code size comparisons with a RISC-V extension that adds multiply/divide and it get really close to ARM: https://riscv.org/wp-content/uploads/2019/12/12.10-12.50a-Co...

My understanding was that RV was less dense than the ARM-M Thumb variants, but more dense than AArch64 like these servers would be.

Yes, you are correct. Thanks for pointing that out to me.

With compression and the multiply/divide extensions very similar to the ARM-M Thumb variants in code density.

https://riscv.org/announcements/2016/04/risc-v-offers-simple...

https://riscv.org/wp-content/uploads/2019/12/12.10-12.50a-Co...

Really fun time to be working on this part of the stack.

The paper you linked to is about embedded controller micro-benchmarks being worse by 5-10%; RISC-V's compressed ISA made some tough decisions to improve density on general-purpose code, not just micro-focused on MCUs. On something larger like SPEC, RISC-V is denser than ARM and x86.

The paper/presentation you link to is comparing 32-bit ARM with Thumb and RISC-V. This is mostly relevant to embedded processors, and my understanding is ARM and RISC-V is somewhat equal there.

But for 64-bit, ARM has dropped support for Thumb, while RISC-V still supports compressed instructions. In that case, RISC-V is more dense than ARM. I can't find the numbers for that right now, but I read it just yesterday so I'm pretty sure I remember correctly.

Also keep in mind that Thumb is a mode that the ARM CPU has to switch to, while RISC-V compressed instructions can be mixed with normal instructions.

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