Hacker News Reader

nMigen supports the Lattice ICE40. However, instead of writing you Verilog/VHDL, you write Python that generates the Verilog.

nMigen still requires toolchains, perhaps you mean that iCE40 is just supported by Yosys+nextpnr?

I’m assuming one would use nMigen with Yosys instead of Lattice’s bloated toolchain. That wasn’t clear.