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Comment by raggi | Hacker News Reader

I do wonder about single address space, I've seen a few experimental systems follow this strategy lately and it feels reliant on hardware less defective than we presently have in commodity user gui performance systems.

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IBM i (OS/400) has had single address space, tagged pointers, and an number of other "novel" things in the loop for eons. Many people interact with it daily, indirectly, in most of your big box retail stores (think stores like Costco, Lowes, etc).

Parent did say "it [single address space] feels reliant on hardware less defective than we presently have in commodity user gui performance systems".

OS/400 and successors don't run on this kind of hardware.

Is that kind of hardware going to be available in 50 years?

Given how we don't even have ECC memory, we shouldn't hold our breaths...

In what concerns ARM and SPARC platforms, memory tagging is happening and being adopted by Apple/Google platforms, in what concerns Intel, it was yet again another from their screwups.

Interesting. Do Apple M1/Ax have memory tagging already?

Not 100% there, but pointer autentication is already a step into that direction.

https://developer.apple.com/documentation/security/preparing...

Meanwhile Google is doing the homework for Android.

"[Arm DevSummit - Ecosystem Talk] Improving Your Android App to Prevent Security Vulnerabilities"

https://www.youtube.com/watch?v=zkoOD4hmiGE

And regardless of one thinks of Oracle, Solaris SPARC has had it for ages.

https://docs.oracle.com/cd/E37838_01/html/E61059/gqajs.html

They're not without their share of critical hardware bugs too, e.g. CVE-2020-4788

I'm curious about tagged pointers, do those relate to the single address space design? Might you or someone else have any good links on this?

You can start by the links on my comment, https://news.ycombinator.com/item?id=25743690

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