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Comment by SoSoRoCoCo | Hacker News Reader

> 3-5 times behind TSMC lithographically,

I'm not entirely sure that is true. TSMC plays fast and loose with their definition of node. Any fab folks want to speak up?

What I mean by that:

https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-n...

"And also goes some way to explaining why, despite TSMC offering a nominally 7nm process, the general consensus has been that Intel’s 10nm design is pretty much analogous. But what’s 3nm between fabs? At that level, probably quite a lot. But if the 7nm node is more of a branding exercise than genuinely denoting the physical properties of that production process then you can understand why there’s supposedly not a lot in it."

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Every fab plays loose and fast with the terms, including Intel these days.

More or less TSMC 7nm := Intel 10nm, and TSMC 5nm := Intel 7nm. It's more complex than that, one has denser logic while the other has denser SRAM and what have you, but it's a good baseline.

Since Intel is struggling with 10nm but is shipping, that puts TSMC about a node and a half ahead.

If you want to dig in deeper, wikichip has most of the public specifics on the process nodes (which are heavily shrouded in secrecy). For instance: https://en.wikichip.org/wiki/7_nm_lithography_process

Ah, good info. Thanks.

Intel can't get good yields at 10nm.

Yeah, that's why I counted it as a half node. Shipping, but awful yields. Meanwhile N5 is doing better than N7 at the same time in lifecycle from a yield perspective.

https://en.wikipedia.org/wiki/Transistor_count#MOSFET_nodes

Look it up yourself. Intel being on 14nm vs (say) 5nm is actually quite flattering to Intel.

That only lists the number, not what the # actually means in terms of actual lithography or more importantly, transitor performance. It used to be minimum feature size, or just L of the gate, but with finfet it can be an overloaded term. Scaling in x of .75 and y of .7 lead to 10% performance improvement per node at Intel. TSMC hasn't been that clear. And that doesn't even account for increase in metal layers, pitch of layers (or if they use poly lower layers to get even faster gains), or average track density due to above/below electromigration minimums.

EDIT: All of this stuff is usually stated at ISSCC every time a new process is announced, so it isn't NDA. I haven't followed this in years which is why I was asking for a process person to step in.

And what information is there that isn't under NDA?

Everything in M1 and everything on Intel 14nm. Go read wikichip. It is there. IEDM just happened, tons of detail there.

3nm, sure, good luck.

Intel 14nm is 42/70/52 (fin/cgp/mmp) with a 7.5 track height. HD stamBitcell is 0.05um2 Very restrictive design rules

Tsmc 5nm is 27/54/36 with a 6T and 7.T option. More open design rules. HD SRAM cell is about 0.025um2.

This is almost exactly what you expect for 1 node of litho scaling.

The more difficult part is that the designs and related process optimizations for intel are different.

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