I wish there were a good tutorial about FPGA development using version control tools. It’s easy having Vivado project with couple source files, but totally uncool using block design. Especially with my own IP blocks.
However, managing a Tcl script is very doable, and this is my preferred method now. This has some drawbacks too of course -- you have to ensure that you use the same arguments to the `create_bd_tcl` command every time you update your script, and if you need to make any modifications to the script then you need to have a process for doing that. But it's much better than the alternative.