This is fascinating work, mate. I wouldn't even know where to begin! Any plans to implement something like a RISC-V instruction set in the future? :)
* https://hackaday.io/project/18491-worlds-first-32bit-homebrew-cpu
* https://hackaday.io/project/178826-pineapple-one
* https://hackaday.io/project/18859-risk-vee
* https://hackaday.io/project/168894-rv7400-computer
* https://www.youtube.com/playlist?list=PLEeZWGE3PwbZTypHq00G-yEX8TEI95lw4
There are lots of soft cores available for RISC-V too of course.