Now they got a solution to add hundreds of megs of cache for cheap.
More importantly SRAM can be binned/tested/KGDed separately!
And it can be fabbed on its own customised process!
And also, they can throw in an eDRAM there instead on a moment notice.
And as they already have silicon interposer here, adding HBM2/3 will be also a triffle.
See Intel's Foveros https://www.anandtech.com/tag/foveros or Ponte Vecchio that they've been talking about for 2 years now ( https://www.anandtech.com/show/16453/intel-teases-ponte-vecc... )
Plus there's an upper limit to the computing power that people need from their phones as well, so the sleek ads for phones simply don't work on many people nowadays. They are content with what they have.
They can seriously reduce the L3 cache area, which is like 50% of the die currently, or get rid of it alltogether.
Imagine, 2 times more dies per wafer at near no cost except for extra packaging.
If a particle kills a repairable part of the die (which can be downgraded, or cut-off) you still get from a quarter, to a half of die area dead, and a second grade chip.
But if you can make 2x dies from wafer even with the same defect rate (it will usually be less.) Even if the die will completely die from a local defect, you still get much more perfect dies in total, which is more important for your bottom line.
Standalone SRAM can be very repairable, and high yield with a custom process. Adding few spare columns, or SRAM banks should be covering for much more defects than if binning was done per entire CPU die.