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Comment by 55873445216111 | Hacker News Reader

Really impressive and a plesently surprising feature from AMD. I imagine the real target market for this is Eypc server CPUs. Eventually they might be able to cut the L3 cache out of the CCD die completely and rely only on external SRAM die as L3. This would give AMD a very flexible portfolio where they can offer different SKUs with different amounts of L3 cache at different price points, all using the exact same CCD die. What will be interesting is to see how much the die stacking impacts thermals.

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Also consider that cache is typically a substantial portion of the die, that's some impressive cost savings to be able to etch the wafer without having to worry about the greater area with cache resulting in a potentially defective chip. Smaller chips, more chips on a wafer, less loss overall with a defect.

the first thing they did in the presentation was show a 12% gaming FPS uplift.

market is anyone who wants faster stuff.

But yes, databases will love it, so will compilers.

>> Eventually they might be able to cut the L3 cache out of the CCD die completely and rely only on external SRAM die as L3.

That might also reduce latency? They've got all these cores around the cache, but in this case it would be directly above all the cores. Seems like it could reduce the maximum distance to cache. But then you'd need even more cores to keep the die sizes similar :-)

It wouldn't surprise me if they have a really expensive epic chip with 8 cores and 1gb of cache. A chip like that would be incredible for applications with per core licensing

1GB on-chip SRAM is quite feasible at 7nm according to several companies designing a single chip ASIC for Grin's Cuckatoo32 Proof-of-Work, that needs 512MB of sequential access memory and 512MB of pure random access memory for a maximally efficient solver [1].

[1]https://forum.grin.mw/t/cuckatoo32-feasibility

Also for APU. APU's GPU performance is heavily constrained by RAM bandwidth.

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