Not quite.

DDR4 and DDR5 have 50ns (single socket) to 150ns (dual socket) latency.

For a 3GHz processor, that's 150 to 450 cycles.

On any latency bound problem, SMT helps. However, what you say is true on bandwidth bound problems. Given the shear number of pointer hopping that happens in typical OOP code these days (or python / JavaScript), I expect SMT to be of big help to typical applications.

DDR5 will double bandwidth in the near future. But that's not enough: HBM and GDDR6 have a possible future because you can only solve the bandwidth problem with more hardware. No tricks like SMT can help.