Comment by mdasen | Hacker News Reader

Comment by mdasen | Hacker News Reader

I'd be more interested in hearing about the terms of the Qualcomm deal. Is Qualcomm putting its eggs in the Intel basket for 2025 or has Intel reached an agreement with Qualcomm that Qualcomm will buy from them if it fits Qualcomm's needs and it's ready in time?

If the agreement is "Qualcomm will send some of its business Intel's way," that isn't a huge vote of confidence. Heck, are we talking about Qualcomm's Snapdragon 8xx series or just some Qualcomm chips like the ones they put in WiFi routers? Or their low-end Snapdragon 4xx series?

The article is kinda spinning it as "Intel will be making the Qualcomm chips going into everyone's phones," but it could be more "Qualcomm is going to have Intel manufacture its low-end stuff which is always behind tech-wise and Intel is giving them a big discount because Intel needs a win."

> In the chip world where smaller is better, Intel previously used names that alluded to the size of features in "nanometers". But over time the names used by chipmakers became arbitrary marking terms... This, he said, gave the mistaken impression that Intel was less competitive.

They are definitely less competitive at this point. Nanometers might not be the right measurement, but one can measure transistor density. Maybe that would make more sense?

Even if "Intel 7" (10nm Enhanced SuperFin) is equivalent to TSMC's 7nm, we saw TSMC's 7nm back in 2018. I have a TSMC 5nm in my pocket. I guess if Intel can keep to its road map, it will catch up. If "Intel 4" comes out with products in early 2023, it won't be far behind TSMC's 3nm process (which will likely debut in the 2022 iPhone).

Of course, we'll have to see how well these Intel chips perform. We should be able to benchmark Intel 7 processors with Alder Lake processors landing later this year. Will these stand up well against AMD's 7nm Zen 2/3? Will they stand up against AMD's upcoming 5nm Zen 4? I guess we'll be able to test Intel's chips against what AMD has been shipping and see how well Intel 7 stands up against both 7nm and 5nm processes.

Disclaimer: Qualcomm employee with no inside knowledge of the terms of the deal, opinions are my own.

Generally fabless semiconductor companies use a variety of foundries and processes for their products. It largely depends on the technical requirements of the particular project as well as the cost of the node. In the early stages of a product development cycle, the team will choose a foundry/process and stick with it to the end. In rare cases the process will switch mid-stream, but this is costly because design essentially has to start over. (For digital, this would be after RTL is frozen; for analog/RF, a change at any point requires starting over)

Sometimes, second sources are added after the first source is in production. These tend to be the lower cost fabs like SMIC or UMC, but they in turn design their processes to be drop in replacements for top fabs like TSMC and Samsung to make it easy to switch over.

Given the above, and that Intel's process is not aimed at copying TSMC/SEC, I would guess that you'll slowly see a handful of non-critical products rolling out on "Intel 7". If the process turns out to be performant enough, you'll see more, even possibly higher end more critical product lines. Don't forget that Qualcomm isn't just about Snapdragon. There is a boatload of RF, Power Management, IoT and WiFi as well.

would you mind sharing a bit about what a process implies for the design? ie why does switching a process require massive design changes

thank you

It doesn't necessarily require a massive design change. The problem is that nearly every aspect of two different processes is different, even when there is supposed to be an "easy" migration path, such as when the new process is just an optical shrink of another process.

Specifically, the transistor properties are different, and so are the properties of the tiny metal wires connecting the transistors together. Once you get to the design phase where you're dealing with individual transistors (for analog this is right off the bat; for digital it's once you get to place & route), you spend thousands of hours simulating the behavior of the analog circuits, or the effects of the particular arrangement of digital logic gates, to make sure everything works. When the transistor and wire properties change, you at minimum have to repeat all of that verification

Sometimes, the new process is different enough that an old design no longer works, and it takes a lot of engineering effort to fix it. Other times, a few small tweaks are enough. In some cases, particularly for digital-only ICs, the foundry will validate the migration between two processes, essentially saying, "we guarantee the IC you already designed will just work in this new process". Smaller companies might just go with it and accept any yield fallout, but bigger companies like Qualcomm would probably do their own independent verification.

so if I can summarize -- what we think of as a logical transistor starts to have all sorts of physical properties, some dictated by the material, the physical layout, and probably what's near it. Designers spend piles of time simulating this, and a process change requires that work to be redone.

Thanks again!

You got it right. Translating from a logical design to a physical design requires following rules laid out by a foundry for a given process node (5nm, 7nm etc.). To check if a physical layout confirms to a node, Design Rule Checking [1] is performed as part of the Physical Verification step in EDA [2]. The simulation/checking is highly complex and takes hours (sometimes days) even with sufficient parallelization. Once a design passes the checks, it is deemed ready for manufacture by the foundry.

[1] https://en.wikipedia.org/wiki/Design_rule_checking

[2] https://en.wikipedia.org/wiki/Electronic_design_automation#A...

ty!

I have been doing semiconductor digital physical design for over 20 years

The Verilog RTL for the digital portions of the design are often identical for the same design in 2 different foundry processes.

The combinational logic gates (AND/OR, registers, etc) are made out of transistors and the transistors are different so all of the logic cells are different.

The foundry gives you a library with these cells. You use a synthesis program to "compile" them from Verilog to logic gates.

One foundry may have 16 different types of AND gates of various sizes, drive strength, and power usage. The other foundry may have 14 types but their 14X cell is stronger than the 16X cell of the other foundry. There is no direct mapping between these.

One foundry may make all standard cells 200 nm in height. They are then placed in uniform rows by the automatic placer tool (Cadence Innovus or Synopsys IC Compiler)

The other foundry made their cells 220 nm in height. The block sizes in your floorplan are now going to be different.

One foundry made their process for their internal mobile phone use so they focused on small cells for low power. Now you try to make your $3,000 GPU in this process and it won't work as well.

One foundry made metal layers 1-5 thin and 6-10 thicker and 11-15 really big. The other foundry had metal layers 1-6 thin. In your old chip you decided to use metal 6 for a certain power layer. Now it is thin and it isn't good for carrying power but thin wire is better for signals. More stuff to change.

It gets even worse for custom analog stuff like a PCIE/USB Serdes or PLL. The rules are even more different. You may need some high voltage area and a larger spacing between that section but the other foundry let you put it closer together.

In my experience TSMC is the easiest to work with. They have a huge infrastructure to help external customers.

Samsung foundries are mainly used by Samsung so they aren't great to deal with as an external customer.

Intel only has external customers for strategic things like Altera which they bought 2 years later. Intel optimizes their DRC rules to make one chip a billion times. Their DRC rules are very restrictive to optimize yield. This takes more people and time.

TSMC is optimized for a thousand customers making a thousand different chips. They don't care if your yield is 1% lower and you probably don't either if you can get to market 3 months earlier with 10% fewer employees.

For Intel that extra 1% over a billion chips is worth hiring more people to meet those extra DRC rules.

thank you -- I built a (tiny) processor for class with Mentor Graphics, but laying out logical gates was as far down as I went. This is really fascinating and thanks again for sharing.

Given that almost all previous Intel foundry customers have failed, why should we expect a different result this time? Achronix is perhaps the most telling as FPGAs are incredibly regular and should have been a natural fit for Intel's manufacturing capabilities, but even Achronix ended up moving to TSMC.

Right now Altera FPGAs seem to have the same supply constraint issues as Xilinx at present (my favorite check is to look at stock levels on Digi-Key), so I'm getting the impression that Intel is unable to crank them out any better than other foundries. Furthermore, if Intel really was determined, I'd have expected more than just a handful of Altera's SKUs to be on Intel's process 5.5 years after acquisition.

My faith in Intel is not strong on this front. Does anyone else have reason to believe this time will be different?

For analog/RF, Qualcomm would need a larger node than 7nm, as I doubt Intel has ready-made blocks for 7nm RF/analog.

The Qualcomm chip digital part would be manufactured by Intel, and the analog/RF part by TSMC? I don't understand how that would work...

I'll tell you of a story of 5-6 years ago.

There was a company called Allwinner Semiconductors. It was making super cookiecutter SoCs for tablets, and been aiming at the exploding "phablet" space.

In the tablet space, it completely vanquished companies with many times the market cap, and marketing expense Qualcomm included.

Qualcomm was really scared of them following them to the smartphone space, and going for their jugular.

What they did:

In around 2015-2016, they announce a "strategic deal" with Allwinner, with Allwinner distributing their low end SoCs on a borderline giveaway terms.

Just few days later, their "phablet" offering disappears from their website. Few month later, their C-levels leave the company one after another, with some leaving for the fancy life in the US.

I had contacts of some of their management people in my wechat account, and after 2016 their feeds were all cheese, and wine, cheese, and wine, and fancy dining, and parties.

Nowadays, Allwinner is a shadow of its former self in its heydays, mostly dealing with most basic settop box SoCs.

Timeo Danaos et dona ferentes

I miss the days of weird phones and tablets with brand names I've never heard of with Allwinner SoCs in them. Such odd devices, so much fun to play with and explore. Rockchip based handheld gaming devices are about the closest to it nowadays.

Doesn't the Pinephone, HN's favorite mobile device, use Allwinner SoCs?

Yes, but that's not what the poster is talking about. The Pinephone is a comparatively conventional/mundane handset design. It sounds like they were longing for more 'out there'/experimental designs that apparently were using A64 several years ago.

how about MediaTek? is Qualcomm worry about MediaTek?

The momentum has been lost.

Mediatek is a much more conventional vendor than what Allwinner was, moreover a Taiwanese company without advantage in mainland China.

I think Qualcomm is quite used to competition from such.

Sounds like a good deal?

Laocoon !

Sad. I wonder if Allwinner A200 will ever be released or is even being worked on...

> but one can measure transistor density. Maybe that would make more sense

Though by stacking 2D layers they can artificially balloon their density figures: 7nm is nominally ~95 million transistors per mm2 - but stack two of them and you can boast having 185MTr/mm2

I just found this: https://www.reddit.com/r/hardware/comments/bx9408/how_does_i... - so yeah, numbers are meaningless

Related: The node is nonsense (https://ieeexplore.ieee.org/document/9150552)

Different number have different amounts of meaning. The technology is so incredibly complicated at this point that coming up with a single number that can be used for meaningful comparisons doesn't appear to be possible.

The nanometer measurement was used to measure the whole transistor and when it was becoming harder to go smaller the nanometer measurement was changed to the smallest feature you can make on a silicon, so the competition is now who can make the best transistor.

No one would make WiFi router chips or even low-end smartphone processors on these processes.

Not sure why you're being downvoted, you're absolutely correct.

The low-end 400 series is a good 1-2 processes behind, being 11nm currently with the Snapdragon 480 5G (2021) on what looks to be Samsung's 8nm (aka, Samsung 10nm+), and the Qualcomm 215 (2019) is on 28nm even.

Qualcomm isn't going to buy bleeding-edge foundry space for a low-end product, and definitely not for a wifi router which has almost no power or significant performance constraints.

They never said which process the foundry services will provide, it's entirely possible they'll use the extremely mature 14nm++ process.

the article did say it, Qualcomm will be using the Intel 20A process.

here's a better article, but the Reuters article did include the point about Qualcomm using Intel 20A.

https://www.businesswire.com/news/home/20210726005136/en/

My (limited) understanding is that a lot of beamforming / MIMO techniques are limited by the power budget of the WiFi chips. So if you could use the fanciest processes, the WiFi chips could be better. I don't know if that's worth the price (everyone expects WiFi to suck 24/7), or if the process helps there, but it does sound like manufacturing technology, not math, is the limiting factor for WiFi right now.

Having extra chains is a ton of power, but it's also analog stuff - that's already not what cutting edge processes are for.

Intel 7nm should be equivalent to TSMC 5nm and should be launching some time soon (if not already). It didn't seem to bite off too much new stuff at one time like 10nm did, so I doubt it will see the same delays.

Intel's fab woes are starting to lessen. I have little doubt that they'll wind up leading the pack again in the next couple years. I hope that this time around there are more companies that can use those advanced fabs.

for fabless company like Qualcomm/Nvidia. the cost of chip production is a factor. they needs to get the lowest cost that is possible.

Apple on the other hand needs the latest tech to sell their product. Apple don't sell chip.

Wasn't Qualcomm announced as a 20A customer?

For those who don’t know, that’s 20 angstroms (1 Å = 0.1 nm, or 10⁻¹⁰ m)

Pedantic but Ångström the Swede’s name -> Å, but US keyboard -> angstrom

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