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Comment by shadilay | Hacker News Reader

I wonder if they'll call it "glued-together". https://www.pcgamer.com/intel-slide-criticizes-amd-for-using...

The 4 die SoC does look an awful lot like 1st gen EPYC.

It's especially ironic because Intel had also previously "glued together" chiplets for the C2Qs and their equivalent Xeons (e.g. X3200 series).

> The 2 × 2 "quad-core" (dual-die dual-core[17]) comprised two separate dual-core die next to each other in one CPU package.

https://en.wikipedia.org/wiki/Pentium_Pro

> Later, it was reduced to a more narrow role as a server and high-end desktop processor and was used in supercomputers like ASCI Red, the first computer to reach the trillion floating point operations per second (teraFLOPS) performance mark.

Amazing. RTX 3090 has peak fp32 performance of 35 TFLOPS.

I believe that almost all floating point instructions on the Pentium Pro had the same performance whether you were using the x87 FPU in 32-bit, 64-bit or 80-bit mode, so it's probably more fair to compare ASCI Red against the fp64 performance of today's GPUs. NVIDIA usually doesn't let the consumer GeForce parts get anywhere near 1 TFLOPS for double-precision. You have to look at some of their Titan or datacenter GPUs to get that kind of double-precision performance.

And at the time of the Phenom X4 launch, AMD was mocking Intel for not putting all cores on one die. Seems the technically superior solution wobbles depending on who's doing it.

Chip development cycles are long enough that sometimes the only response companies have is to downplay their competitor's innovations until they have their own version. The hilarious part is that sometimes it works.

Though there's something to be said about die size. If you can't reach 250mm2 on a single die, that's much more mockable than wanting multiple dies to build your 900mm2 server CPU.

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