Cache splash in Telum means seventh heaven for POWER11?
talospace.com
talospace.com
It would be fun to build some Network on Chip FPGA designs using this approach to model how it would perform!
But I'm curious what sort of algorithm you have in mind that needs to spend a lot of time moving data between cores. Maybe some sort of algorithm that needs to alternate short steps of aggregating intermediate data and re-distributing the result to every core, in a loop?
So, the shape of the problem that would fit this solution is not obvious to me :)
Embarassingly parallel algorithms are the ideal. The less communication, the less Amdhal's tax costs you.
That's quite competitive with AmigaOne once you account for the far better performance you get with the Talos. Run a free AROS operating system on the board and you've got a great, future-proof machine for all sorts of uses.