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Comment by _V_ | Hacker News Reader

> A lane is composed of 2 wires: one for inbound communications and one, which has double the traffic bandwidth, for outbound.

I might be wrong, but I believe PCIe lanes are differential. Meaning you have to have 2 pairs of wires (1 for each direction), not 1 totaling 4 physical wires per lane.

Also both pairs in the lane should have the same bandwidth but since they are "full duplex" system, you might say it doubles the overall bandwidth of the lane but it does not mean that one of them is twice as fast.

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Yes. Every lane has 4 data pins. TX+, TX-, RX+, RX-

The data is transmitted and received as differential pairs because this helps in signal integrity issues.

You are also correct that you can transmit and receive at the same time but whether this helps our now depends on what you are running.

The Serdes used for PCI-E are also used for other protocols like SATA and USB3. They are extremely similar at the physical layer but the higher layer protocols are very different.

USB 1/2 has a single differential pair so you can only transmit or receive but not at the same time.

USB 3 has differential pairs for RX and TX so you can do both at the same time.

> USB 1/2 has a single differential pair so you can only transmit or receive but not at the same time > > USB 3 has differential pairs for RX and TX so you can do both at the same time.

Just in case this leaves some readers thinking it's only possible to transmit or receive on a differential pair, not so:

Copper gigabit ethernet (1000Base-T) transmits and receives at the same time over all four differential pairs, using adaptive equalisation and echo cancellation to separate the outgoing and incoming signals on each pair.

The signal processing is quite power hungry, and doesn't work so well at higher speeds. So it makes sense that PCIe wouldn't do this.

You are not wrong I can’t tell if this article is some machine learning written garbage or a Dunning–Kruger effect thesis.

It literally starts with a discussion about add-in cards form factors like it even matters. Then has tons of blunders, like the full/half duplex one, calling transfers / second frequency which it isn’t how many transfer a second has little to do with the clock frequency because it’s dependent on many other factors such as the width of the channel and how many times per clock cycle you can transfer data. It doesn’t even begin to go over the basic concepts of the PCIe root complex and the structure of a switched fabric.

Then I has some gems like “having a nice GPU with 16 PCIe Lanes and having a CPU with 8 PCIe Bus lanes will be as efficient as throwing away half your money because it doesn’t fit in your wallet.” which really isn’t true…

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