Just like Nios II, it's a processor. It doesn't have to be "hard" silicon. Calling it a "little FPGA program" seems very dismissive. I don't know what you mean by "1990 style".
They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to.
> Calling it a "little FPGA program" seems very dismissive.
Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.
I haven't made a production IC, but I'm told that's much harder. I would be awesome if Intel made a RISC-V chip, even a slow one just good for arduino-type toys, but that's not what happened here.
There's a lot of processors out there. The vast, vast majority being shipped are in order and a handful of stages.
> Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.
> I haven't made a production IC, but I'm told that's much harder. I would be awesome if Intel made a RISC-V chip, even a slow one just good for arduino-type toys, but that's not what happened here.
The FPGA vendor provided soft cores have about the same amount of engineering rigor as a hard core. They have enough customers for the designs to have enough reach to have the same financial implications for bugs.
The FPGA vendor provided soft cores have about the same amount of engineering rigor as a hard core.
Intel has a terrible track record with maker-ish stuff. They routinely launch products, sell them for a year, then discontinue them. (Intel Euclid vision SBC, Intel Edison x86 microcontroller, the realsense stuff, etc)
You can't build an ecosystem around a product if you kill it after a few months. Arudino is only Arduino because they actually stuck around.
Providing a good FPGA CPU to run all the custom stuff is a great way to sell more chips.
This isn't aimed at makers so much as aimed at huge corporations with loads of money to burn on FPGA hardware, circuit design, and custom software.
You can still buy tons of 386EX chips and boards on eBay and even a couple first-hand (JK Flashlight) and there's a few modern homebrew designs out there.
Probably completely overkill for a soft-core.
On top of that, designing and verifying a core that people actually want to use is obviously much more difficult to do than going through HLS.
That's inefficient for an FPGA softcore; wires are too expensive, CAMs are straight up awful, and memory latencies aren't too far off relative to the core clock frequencies to justify OOO stuff in the normal case.
> Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.
Writing a 5 stage is easy.
Writing a 5 stage with no bugs is much harder.
Writing a 5 stage that talks industry standard busses and provides Debug/JTAG Support at high frequency and small gate counts is, well, an actual job.
Not saying you can't do better, but it's not a trivial effort.
This is meant to compete with Cortex-M1 and MicroBlaze, not with Cortex-A78 or Core i9 or something.
You get the core you need that meets the processing budget with as little cost, area/resources needed and with as little power consumption. That was true then and it is just as true today.