Hacker News Reader

HNHacker News

Top New Best Ask Show Jobs

Comment by jleahy | Hacker News Reader

Parent Full thread

jleahy·

Both are awful languages, but Verilog is an awful language with broad industry support.

View on HN

VHDL and Verilog both have industry support. VHDL is much better if I had to pick one though.

It seems to be though a lot the open source stuff seems to pick Verilog for some reason.

Most commercial tools support both HDLs.

While Verilog is not SystemVerilog, it’s more or less a subset of it. And SystemVerilog had much more industry support for design verification. So if I were to design some open source software for HDLs, that reason alone would make VHDL a non-starter.

SystemVerilog and UVM are perfectly capable of being used to verify VHDL designs.

I should also add that if you wanted to use a single language for everything OSVVM is excellent.

Sure it's capable, but there's certainly a cost of having to use multiple languages in your test bench/DUT. I'd argue that's one of the reasons why Verilator, CocoTB, Chisel, etc. haven't taken off in the "traditional" semiconductor industry (i.e. not FPGAs).

Verilog is now officially the subset of SystemVerilog since 2009 [1]. The same can be said now for C since it's supported in both C++ and D compiler.

[1] https://standards.ieee.org/project/1800.html

Tools support both, but the vast majority of companies are using (system) Verilog for design. VHDL shops do exist, but are rare.

My understanding is that verilog is more popular in us while vhdl is common in europe/germany

Well I’m in the UK and it’s also true here, I don’t know about Europe proper.

Reply on news.ycombinator.com