Mixed instruction set schedulers? Intel 12th gen issues | Hacker News Reader

Mixed instruction set schedulers? Intel 12th gen issues

3 pointsdoommius5 comments

I've been looking a bit at the news recently about the intel 12th gen CPUs, and how they disable the AVX-512 instruction set if the efficiency cores are enabled. which seemed like a weird and poor implementation that bottlenecks some workloads and leaves quite a bit on the table in terms of performance. Why isn't this handled in the scheduler ? all the major operating systems already support the big/small core design. Why isn't the instruction set requirements simply passed to the scheduler via program headers to dynamically schedule tasks in the most efficient/fastest manner?

I read a bit up on the topics and there is already research into the topics. so I wonder why the approach intel used is even there. http://web.cs.ucla.edu/~tjn/papers/pact2018-hybrid-sched.pdf

Why isn't a better solution used? and why just disable the functionally as it seems like low hanging performance gains from intels side? And isn't this a approach to also look into more as modern hardware utilize ASIC style or dedicated hardware for more operations and will so going forward?

There is no facility to say "this program runs AVX512 instructions". For that matter, a program may not know that it does. If it uses a JIT, loads a dynamic library, etc.

And if you mess it up, you get an invalid instruction, so that is something that you really want to avoid.

Agreed, but there has to be a better solution then just outright disabling the features.

Intel is not 100% serious about quality and performance.

The Whole AVX1, AVX2, AVX4, …, AVX8192 means the SIMD instructions will only get used by missile labs. Since you have to recompile all your code to use them and because end users will have old machines, devs will either stick to something 10 years old or just skip them entirely.

It is self-defeating for Intel because their greatest competition is not AMD or ARM but sticking with the CPU you already have. Hypothetically SIMD is the major source of performance improvement in new generations but if the software doesn’t support it, it might as well not exist, so why upgrade? If users don’t upgrade why should devs use the new SIMD instructions.

Try to tell them this common sense and it is just ‘talk to the hand’.

True. True, it'll only be on the server side market. but didn't intel just buy Centaur with their AVX-32768 as well? but again, probably for use in server side or their GPUs.

I assume for higher level AVX support we'd need client side compiled code or multiple binaries with different compile flags. which is quite doable today, as everyone downloads software from services like apple store, windows store, steam, adobe, AutoCAD download manager etc. so client side it shouldn't be a big issues anymore. the downloader will just fetch the optimal binary for the platform you're using?

The invalid instruction can be caught by the kernel, which can inspect the instruction, see that it's avx512, mark the process as avx enabled, and only run it on p cores.

Some sort of settings or policy could be set up so that processes don't force themselves onto the p cores.

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