Having a thorough understanding of the process, I thought this was hilarious. But if you really want to understand the process, it's pretty terrible. It spends 10 steps on making a wafer, and then the bulk of the actual process is condensed to 16.
I'm going to guess at a number and say you're probably looking at $10-20MM all in.
As far as hiring good designers, you really need the relevant technical background to screen them. Assuming you need a team, I would suggest starting with someone in a director position at a large company with experience in your area of interest. They would be able to more concretely define the project and determine human resource requirements/allocation.
If your ASIC is just large but not complex (meaning lots of repeated structures), and you can get away with just a few strong designers, I would suggest hiring a consultant to help you define the project and screen candidates. EE profs at your local university might be a good start.
Feel free to shoot me an email (in my profile) if you want to describe your project in more depth and I'd be happy to offer what advice I can.
7nm logic mask set costs are estimated at $10.5M. Of course you could always use a slightly less leading-edge node and save a lot of money.
Slide 13:
https://semiwiki.com/wp-content/uploads/2020/03/Lithovision-...
To put it in perspective, a company a friend founded that is doing a very large but very regular ASIC for TSMC 10nm raised twice what you're ballparking and will end up doing another raise before tapeout. Chips nowadays are _expensive_ if you're anywhere near state of the art. The people who do very high performance chips are also very expensive.
But I'm also guessing that unless you're doing a bitcoin hashing chip, AI chip, or GPU, all of which is regular, your scale estimate is probably very off. If you're doing any of those, just don't.
That said, there are SOC vendors who do core plus, so it's possible that if this is just an accelerator, no matter how wide, you might be able to outsource the whole thing.
May I ask why?
I was into hobby chemistry for a while -- people trying to do anything in the EU find it almost impossible. Poland and Eastern Europe are better about it, but eh.
I rather think that Cody is a bad influence, of the kind that could attract unneeded regulations.
Integrated circuits are appealing to industry because they're integrated - they can be smaller and they reduce cost (long term; still need the upfront investment). These are important things for many products, especially in RF, but they aren't really driving factors for hobbyists.
That being said, people are trying! http://sam.zeloof.xyz/second-ic/
If it means designs inside an EDA environment, design get submitted and shows up realized, then that is possible now. And it's not all that expensive. eFabless chip ignite is quoting ~$10K for 100 QFNs in 130nm. That's getting into beater car territory. https://efabless.com/chipignite/2110C
If it means actually fabricate then I think there is no way because a DIY won't have the scale to compete on price and they won't be able to bring any custom processing step to justify being at boutique scale. Think about PCBs. We used to make them ourselves with chemical etch. Now I don't even use breadboards because a custom bare fab is $5 and the components cost more than that. I also get a much better electrical result, and it doesn't fall apart if I look at it funny.
The main problem with ASICs is the amount of skill/time that it takes to do it right. Floor planning, track planning, closing timing, etc. etc. on an ASIC is much harder than an FPGA. You don't even have to do half those things on an FPGA.
With an FPGA one can almost get compile and go if you're willing to be loose on area and performance. ASIC CAD tooling is no where near that at the moment. Closed or open source.
Then you do the lithography (photoresist developing, etching, etc) to expose specific regions on the silicon that you want to dope to create devices like transistors, for example. So first you might expose all of the p-type transistor (PMOS) diffusion areas and dope them. Then you'd remove all the photoresist, repeat the procedure to expose n-type diffusions and dope that. And so on for the various needs of that particular wafer.
PN junctions are created simply by having p-type doped silicon adjacent to n-type doped silicon. The boundary between the two is the PN junction. In practice what I usually see is a square of one type with a ring around it of the other, but these devices are not frequently used.
Do you use any countries or specific factories that do better refinement or are the raw materials directly shipped to the manufacturing country? What do you make from the wafers usually? Are certain sizes much harder to make? I know for example that larger sensor for digital cameras are much harder to make. I also heard of redundant circuits used to increase the yields of chips, how often is this used and when is it most useful versus less?
Another issue is the equipment used for manufacturing. It's very hard to come by, and the classic example is ASML (Netherlands), which dominates the market for lithography equipment.
I work on the design side, not in a fab, so I can't tell you much about sourcing or refining the silicon for wafers. Wafers are used to make every single microchip you can imagine. There has been a slow but continuous push towards using larger wafers, since its more cost-effective. I imagine it's more difficult, but couldn't tell you any specifics.
As far as manufacturing each individual integrated circuit: yes, larger is harder to manufacture because there is more physical space for a defect to occur. There are some design challenges as well when you get very large, but it's not a significant overhead because you're usually doing your design in sub-pieces anyways.
Some designs do use redundancy, as you mentioned. This is more often the case for very large, very uniform structures, like DRAM, flash, CPU cache, etc. But there's a tradeoff because you waste money on that redundancy for every chip that comes out with no defects. And there's overhead to actually testing the part in order to utilize the redundancy. In my experience, yields are targeted at the high 90%s these days, so the redundancy would have to be very cheap to be worth it. For almost all RF, analog, and mixed-signal circuits, there is no redundancy. I'd say most digital circuits, except the largest, also don't have any.
Also - does the US really have microchip supremacy? The highest tech fabs are non-us (Samsung and TSMC)
>Soviet computer software and hardware designs were often on par with Western ones, but the country's persistent inability to improve manufacturing quality meant that it could not make practical use of theoretical advances. *Quality control*, in particular, was a major weakness of the Soviet computing industry.
https://en.wikipedia.org/wiki/History_of_computing_in_the_So...
On linux, they are making one with an allwinner chip called the D1. https://www.hackster.io/news/sipeed-teases-linux-capable-64-...
RISC-V is not inherently better or more secure, its a different instruction set with no fees, so anyone can make one, its possible to be less secure.
If I had the skills I would immediately investigate how to couple a RISC-V CPU with some open GPU on that platform!
https://www.youtube.com/watch?v=NGFhc8R_uO4
lots longer, but far more informative and less fluffy.
For large digital circuits (e.g. CPUs), it's all automated. There's a lot of human involvement, but ultimately a computer is placing all the transistors and wiring them together.
https://en.wikipedia.org/wiki/Silicon_photonics https://en.wikipedia.org/wiki/Integrated_quantum_photonics
If minecraft taught me anything it’s that ore doesn’t spontaneously turn into ingots.
I haven't been in school for a while, so I'm not sure what's current. I really liked Baker's book - CMOS circuit design. It had a decent overview of the manufacturing process for the perspective of a designer, as well as good introductions to major design topics.
Unfortunately, with modern processes, most of the textbook design equations and learning no longer apply so it becomes as much learning an art as it is science.
Yeah of course when it comes to how things are actually done it's hard to know without actually working in the field. But I just wanted an overview.
And Weste http://pages.hmc.edu/harris/cmosvlsi/4e/index.html
are both very good. Weste is used in more Universities but it also has a digital slant to it.