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Comment by sliverstorm | Hacker News Reader

Let me get this straight. Today, we have trouble dissapating the heat produced by a single die.

To solve this problem, we are going to stack 1000 dies, and produce 1000x as much heat.

Who cares about whether the heat can travel up the column- where is the improvement in cooling technology to remove 1000x the heat from the die stack?

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The point with 3d layout is that you can have shorter interconnects, which means far less resistive heating, and less junction loss. It also means that your path lengths can be shortened, possibly allowing you to bump up the frequency.

Stacking stuff means you should be able to run cooler for the same amount of processing power.

1000x? I think that's probably BS. But I can see this being a significant win.

How about L1 cache (or even just L3 cache) measured in gigabytes? That won't increase the execution speed of individual instructions, but your effective processing power would increase dramatically.

The problem is that as cache size gets bigger, the associative memory lookup gets slower. There's a tradeoff.

What? Why is this, isn't memory indexed for direct access?

We're talking about cache, where the addresses of blocks in cache do not have a 1:1 mapping with addresses in memory.

Read the section on associativity: http://en.wikipedia.org/wiki/CPU_cache

You get to choose your associativity, you could build a direct-mapped 1GB L1 cache if you wanted. More fundamentally, a memory's access time grows with its capacity because the average and worst-case distances from a bitcell to the read/write port are longer.

If you pack enough memory in the same package and connect it to the CPU through a bus that's fast enough, on-chip memory that used to be used for caches can get promoted to main memory and off-chip RAM becomes a fast cache for your SSDs and a way to synchronize context between different chip stacks.

Put the GPU and VRAM on the stack and all you need is a couple HDMI ports going out of the chip.

Cache is already about as fast as you can get without significant compromises in size. L1 cache runs at speeds fast enough that increasing the size (and average seek time), or increasing the distance the signal has to travel, will decrease access times significantly. So it doesn't become about how 'fast' the bus is, or how much memory you can pack on.

Putting a good chunk of memory between the processor and the external memory bus would allow interconnection through a much faster bus than the external one, reducing the penalty of a cache miss.

The two of you are arguing about different things. You are arguing the point of increasing cache to reduce misses. The other guy is arguing that increasing cache size will degrade cache performance as a unit. These are distinct arguments.

This makes me think of an interesting question- the back side of a die is raw silicon. How do you stack die and still interconnect? Do you sink metal through the bottom of the wafer?

Yes, through-silicon vias are metal-plated holes that go clear through the wafer ( http://en.wikipedia.org/wiki/Through-silicon_via ).

IBM talks about up to 100 layers, not 1000. Not all components have the same power requirements or are even powered up at the same time.

Also this is IBM research. They don't need to make robust processors for the consumer market. If the CPU requires watercooling or better, IBM can do and sell that. They already have such solutions for super computers and mainframes in the field.

I would assume the heat would be expected to ooze out the sides of each layer... e.g like the condiments leaking out the burger when you squeeze it :-)

Actually, this makes me think. The area now dissipating heat is much smaller (perimeter of the square * h, and used to be the area of the square). You have to dissipate the heat. The solution really can't be as simple as the article proposes.

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