Deep Diving Zen 3 V-Cache

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Interesting. I expected gaming realed read but this is better and makes more sense as these are likely very expensive to make which is why 5800X3D is the only consumer products that has been announced

Did Broadwell do well in server workloads? Provided it reached the segment, of course. It did surprisingly well in so many tasks

>Did Broadwell do well in server workloads

wikipedia says the edram was only present on the CPUs with irs pro graphics. the edram was intended to be some sort of cache for the GPU.

How does one test the latency and bandwidth of CPU cache at each level?

Pretty easy.

Rdtsc is the read timestamp counter instruction. Every .25nanoseconds, that counter goes up by 1 (assuming 4GHz CPU)

Write 32kB of data and measure how many nanoseconds pass. Done for L1 cache.

Do the same for L2 cache size.

Then do the same at L3 cache size.

Finally do it for 4GB or something that only fits in main memory.

Thanks for the very concise explanation. It seems obvious now that you’ve put it into those terms.

The main "difficulty" is that "Rdtsc" has itself a large execution time, and that modern processors have a very strange definition of "execute".

With retirement queue sizes ranging from 300 to 600 (depending on architecture), your singular CPU-core could very well be "executing" 600+ instructions simultaneously, including "rdtsc".

Under such conditions, the "definition" of "get the current time" is quite ambiguous.

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This isn't a problem with bandwidth. But it makes measuring "latency" very difficult, especially because out-of-order execution means that "proper" latency is largely ignored.

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Because of the out-of-order execution models of modern processors, "reciprocal bandwidth", or "instructions-per-clock" tends to be more important than latency proper.

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