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Comment by krallja | Hacker News Reader

I hope your address bus is three nonads wide (3^3 bits = 128MiB address space).

It would be thematically even better if you used ternary logic, but I’m not sure that FPGA can handle more than two voltage levels.

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haha yes, excellent suggestions! I did think about ternary logic actually but I don't know of an FPGA that supports it. I considered creating like a primitive that burns 2 register bits to approximate it even, and just throw away the 4th state and pretend I have 3-state logic on all the layers above. but i have enough on my hands just trying to get the stupid timing working on a simple CPU. Im not actually a CPU designer so I dont really know what I'm doing lol.

Throwing away 25% of your bits sound wasteful... what you need is a moderately large power of 2 that is very close to a power of 3. These can be found by computing the continued fraction of log(3)/log(2). The sequence of convergents starts thus 2/1, 3/2, 5/3, 8/5, 11/7, 19/12, 46/29, 65/41, 84/53. Some good choices seem to be 2^8-3^5=13 (loses 5%) or 2^46≈3^29 (loses 2.5%).

You can also detect Z state by driving the input high, reading, then driving the input low, reading. If both reads are different, then you have a Z state. Otherwise, the input is the read state.

Of course, drive the input through a resistor.

This is a fantastic hobby project. Have you thought about doing something with the "extra" bit along the lines of tagging bytes for type or garbage collection or whatever like the lisp machines?

>I’m not sure that FPGA can handle more than two voltage levels

There is a high-Z (high impedance) state you can set I/O pins to for a third state, but no way to detect that high impedance state from the FPGA. It's just used to share an output line with more than one pin. You could make a peripheral that could detect the three states though, with a voltage divider and an analog input.

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