Hacker News Reader

Comment by pb82 | Hacker News Reader

The article about the Padauk is interesting. Especially the description of the FPPA feature. Multiple CPU contexts? This sounds suspiciously like SMT to me which would be a total novelty for a micro controller (afaik).

View on HN

ESP32 was released August 2016. I’m not even sure it was the first.

The ESP32 has two separate cores, not SMT. But look at the Parallax Propeller which goes back quite a long way. Also the Padauk is not exactly SMT afaict. It's more like time slicing. The idea of SMT in eg. an x86 is that one thread can run while another is blocked waiting for memory.

Sounds like a barrel processor [1], used to hide latency of individual instructions to allow code to be written without having to think as much about instruction scheduling / dependencies.

[1] https://en.wikipedia.org/wiki/Barrel_processor

The Xmos chips give the programmer virtual time sliced contexts over one or more hardware core(s). Say you have a 400 Mhz base clock and 4 threads, each one would see the wall clock time advance at 100 Mhz. This is useful for having concurrent realtime operations on each hardware thread w/o having to resort to trickery.

These chips are ideal for DSP, phased arrays and beam forming. Most of their devkits are centered around voice applications.

https://www.xmos.ai/documentation/XM-014363-PC-5/html/arch-h...

https://www.xmos.ai/download/xCORE-Array-Microphone-Product-...

Reply on news.ycombinator.com