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Comment by amluto | Hacker News Reader

> For all major architectures and CHERI there is only one address space as far as I’m concerned, but it’s potentially worth opening the door for properly talking about pointers in segmented architectures here.

I regret to inform you that x86_64 (which is probably a “major architecture”) is segmented and has three address spaces. In practice, it has two. In user code, those address spaces are normal memory and TLS and, in kernel code, they are normal memory and percpu memory.

And the proposed scheme in this article is, on first read, amazing. It would make the epic hackery in the kernel percpu code safer (in Rust, anyway). The major caveat is that, for even slightly decent codegen, the address space of an x86_64 pointer should be part of its type, not its value. Even do, this scheme still works:

    ptr.with_addr(usize) -> ptr

has a type! If the input pointer is TLS or percpu, so is the output.

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Segments are somewhat different on x86-64, which uses them to just compute a virtual address that you can just use as a normal pointer. There’s no “fat” pointer really involved here, the segment register just provides a convenient place to stash the base address of the TLS or whatever you’re using it for. This is why you can store a normal pointer that points into the TLS. This is different from segmentation in the past where you could really keep everything in your address space at once, so every use of the pointer required arithmetic, or with CHERI where you need to pass around the full “big” pointer to have the right capability to access the memory.

There are C embedded extensions for separate address spaces. So the idea is not totally new. But AIUI, the C extensions still require some way of converting a pointer in a specified address space to the usual "generic" pointer type where the address space could only be part of the vale.

Just like on the 16 bit days there were near and far pointer extensions on MS-DOS and Windows 16 bit.

And th choice of lovely memory models including tiny, small, medium, large and huge depending on the code and data sizes. Good times.

> I regret to inform you that x86_64 (which is probably a “major architecture”) is segmented and has three address spaces.

Can you say more? I assumed the post was referring to segmentation registers, which are not an x86_64 thing.

amd64 uses segment registers for TLS (such as errno).

https://stackoverflow.com/questions/6611346/how-are-the-fs-g...

Thank you! I love learning about stuff like this but I wasn't sure what to search for. Much appreciated.

hmm i've always just mentally modelled TLS as "yeah the OS slaps a pointer to an array in this one register".

but i guess the difference between "pointer to an array" and "a segment of memory" isn't actually that big?

It’s a funny register: you don’t want to read it (and before Ivy Bridge, user code couldn’t read it). The base is added by the CPU when you dereference the pointer. So code like:

    __thread int array[100];
    array[n] += 5:

Effectively computes the offset portion of array+n and then, using CPU assistance, accesses that memory relative to the segment.

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