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Comment by ajaimk | Hacker News Reader

M1 Ultra has a 3x larger heat-spreader than Ryzen. That’s the entire package and not the silicon chip itself.

Also, let’s not forget that this heat-spreader includes the RAM under it.

Here’s the funny bit: the silicon die for M1 Ultra is actually more than 4x bigger than Ryzen 5000 series. M1 Max was 432 mm2; implying 864 mm2 of silicon. Ryzen 5000 has a 84 mm2 CCD and 124 mm2 IO die.

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I think the Ryzen 6000 laptop chips are a better comparison. They are also monolithic, contain a powerful GPU, and are manufactured on a more similar node. Ryzen 6000 has a die size of 210mm².

M1 Pro is 251.3 mm² with a ~5 TFLOPS GPU and Rembrandt is 210 mm² for 3.4 TFLOPS so the comparison checks out.

It's a slightly better comparison, however Ryzen 6000 is on N6 (which is an optimized N7 process), whereas M1 Max is on N5. N5 is considerably denser than N6.

AMD's next round of APUs on 5 nm will offer a better die area comparison.

I remember reading that at 5nm, electron tunnelling through transistor gates would be a major problem. What happened to that?

I think the do funky stuff with the 3D or 2.5D geometry of the gate so that the surface area (between transistors) is larger for a smaller footprint.

Someone correct me if I’m wrong!

Yes, that tech is called FinFET and it has been in use for many years. The new hot thing is GAAFET (Gate-all-around FET).

5nm doesn’t mean anything is actually 5nm. It’s the “5nm node”

Marketing dept has trumped physics.

That would be the case if 5nm didn't refer to a random feature of a reference planar transistor that is only used to chronologically name the process according to its mathematically equivalent density..

I’m guessing the price scales at least linearly with the size. I do hope the new trend isn’t giant chips because the price and availability would be horrible

It's generally superlinear due to yield effects - this is a bit oversimplified, but in particular, with lithography defects being more or less randomly placed throughout the wafer, a defect in a 100mm2 die impacts a far smaller percentage of the dies in the wafer than a defect in an 800mm2 die. Assuming a constant defect rate per wafer, you'll end up with drastically less usable wafer area with large dies than with small ones.

This was a major reason that AMD was able to price Ryzen so aggressively even at the high end - a high-end CPU is just made of more of the same small dies used in low-end CPUs, albeit requiring a better bin, instead of having to make a much larger single die.

The constant defect rate isn't typically a correct assumption across different products (e.g. different CPU or GPU dies) - different feature designs will have differing defect rates. Maybe Apple was able to design the M1 Ultra's features so that defect rate is very very low, though - I don't really know much about that silicon.

probably this is why they decide to do it as last m1 product, in genera the more you use a process -> less error in the production process happens.

This is probably M1 Ultra is designed to be two M1 Max glued together, more or less.

The M1 Ultra would be at or over the reticle limit as a single die, depending on how much area could be saved by removing the inter-die transceivers.

I don't think that's a deal breaker if you're willing to lay thick interconnects, treating the connection much like you'd treat something like EMIB.

After all, Cerebras made a functional wafer sized chip.

> After all, Cerebras made a functional wafer sized chip.

https://cerebras.net/

Yes, but the Cerebras wafer-chip is a repeating pattern of logic, memory, and interconnect tiles. Each pattern is well under the reticle limit of the process node they're using.

And how many Cerebras wafers have shipped? I would imagine that they can afford to spend more engineering effort in the late manufacturing phase, fusing off bad bits, maybe salvaging some other bits... but enabling such late-stage functional-unit binning requires a larger mesh topography.

Apple is using a design that's at the limit of economic feasibility at the mass-market sales volume they can support. They can amortize the engineering expense down among the single most popular retail item on the planet.

Cerebras is an engineering marvel, but I wouldn't call it a mass-market item.

The Mac Studio more closely resembles high-end IBM POWER mainframe modules.

Stunning that you can just go out and buy one. And you don't need a data center to feed it.

https://www.anandtech.com/show/16626/cerebras-unveils-wafer-...

https://cerebras.net/

But you'd also keep each half of the M1 ultra under the limit.

I'm not saying it's a good idea, because they'd have done it if it was. They clearly know what they're doing.

I'm just saying that it's not an absolute blocker for a design you'd otherwise be connecting over something like EMIB anyway.

... three days later ...

Oh, I see: you are wondering why Apple M1 Ultra, as two chips linked by EMIB, couldn't just be the two chips adjacent on the wafer.

See the difference? Apple knows what their yields are; if they could be sure to get two matched SoC M1 Max chips right next to one another on the wafer, they could punch that pair out and bypass the whole EMIB thing.

I don't know enough about testing and dicing 100-billion-transistor chips to know how expensive that would be.

Is it actually 2 different pieces of silicon though? I thought they were 2xM1 Max as a single silicon. Which wouldn't help with defect rates

It is two separate dice, with an EMIB-style interconnect.

That makes a lot of sense. The Max is still pretty fucking big, but two of those is a lot more manageable than a single monolothic die double the size

I just listened to the latest atp.fm podcast. I think John said that it actually is two adjacent M1 max dies. The Ultra can’t be made from two random working die. They have to physically be adjacent on the wafer.

I don’t know if that means it’s physically one due though.

Usually dies aren't mirrored on the wafer so I'm calling citation needed on this one.

Not sure if the counts. I know it’s a patent and it could be anything. But it talks about two adjacent dies being used if they’re good or being split if there is a defect.

https://patents.google.com/patent/US20210217702A1/en?oq=2021...

Thanks for the link. I'm not a lithography expert, but this looks like a Cerebras-style approach at a smaller scale. It might be cheaper than the EMIB/InFo approach since there's no interposer with the associated alignment and thickness issues. In the keynote Apple explicitly said they're using a silicon interposer, which doesn't sound like this patent.

Apple has both a 48 core & 64 core GPU variant of the M1 Ultra. Since the GPU is the largest single element of the M1 Max / Ultra, that's how they are handling yields. And it's then +$1000 for the 64 core variant over the 48 core, suggesting probably "normal" TSMC yields and then a very healthy profit margin. Apple does have the luxury of just charging whatever they want for this SoC since they are a market unto themselves. So even if yields are bad, they can just pass that cost along to the consumer.

Not entirely unlike what Intel used to do with Xeons before AMD re-entered the picture and what Nvidia kinda does with the likes of the A100.

Yep, It’s a poor comparison, the Mac chip has up to 128 gig of RAM under there, and other stuff like SSD controller, etc..

It is kind of awesome to look at though.

Why not spread the processor across the whole Macbook motherboard, wouldn't this bring huge cooling benefits with no major downsides?

The downside would be latency increase / speed reduction.

Speed of light is something like one foot per nanosecond. So at 2GHz you go 6" per clock, assuming you can actually go the speed of light which, in a wire, you can't.

The whole point of going to smaller nm process is to bring things closer, so it takes less time to move information.

The shorter signals have to travel, the less time and power it takes to do so.

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