I think this is actually not right. There's not any kind of loop that is running, it's triggered by signal edges. That's the fundamental difference between hardware and software that makes hardware difficult for software people. Everything happens simultaneously.
always @(posedge clk) begin
do some stuff
if (condition) begin
@(posedge clk);
do some more stuff
end else begin
@(posedge clk);
do some different stuff
end
......
end
In simulation this is easy to implement, but in synthesis the synthesis tool needs to rewrite it as some hidden flops for state and a top level case statement
always #half_period areg = ~areg;
always c = #5 ~c;
If not, where in this shift register[1], when synthesized to an FPGA, is the loop waiting for posedge clk or posedge reset?
[1]: https://asic4u.wordpress.com/2016/03/28/verilog-1-delay-in-r...
always begin
@(posedge clk) v <= a+1;
@(posedge clk) v <= a-1;
end
always @(posedge clk) begin
v <= a+1;
@(posedge clk)
v <= a-1;
end
Ok, then we agree. Of course a simulator will have an implicit loop, that's not contentious.
However you did not mention this in your initial statement, and I've read and been told explicitly not to think of it like this because there's no loop in hardware.
It’s like programming a machine to make a watch. At the end you have a watch. Would you say the gears execute in parallel while it measures time?
In some sense it’s right, but in another it’s missing the point.