Intel history has quite a few failed attempts to memory tagging (iAPX 432, i960, MPX), maybe it needs again an AMD push to make it work.
Nevertheless, in this case AMD is wrong, without doubt.
Intel has published one year ago their version of "Linear Address Masking", which might become available in Sapphire Rapids.
There is nothing to criticize about Intel LAM. It keeps the highest address bit with the same meaning of today, to distinguish supervisor (kernel) pointers from user pointers.
Address masking can be enabled or disabled separately for supervisor pointers and user pointers. Address masking has 2 variants, depending on whether you choose 48-bit physical addresses (4-level page tables) or 57-bit physical addresses (5-level page tables).
AMD has published now a different incompatible method. It is likely that they have conceived it a few years ago, when the design of Zen 4 had started, which is why it is incompatible with Intel.
The fact that it is incompatible with Intel would not have been a big deal, except that the AMD method is wrong, because they also mask the MSB, breaking all the kernel code that tests pointers to determine if they are user pointers or not.
Like everyone else, I cannot understand why AMD did not specify rightly this feature, like Intel. It certainly is neither rocket science nor brain surgery.
Now Intel and AMD are catching up with this feature. Unfortunately they went separate ways.
This is a trivial feature, which does not have any potential for competitive differentiation.
However, for the users, it is very important for it to be standardized, to behave identically on all systems. It would have been much better if Intel and AMD had discussed this and they had decided on a common specification.
AMD is guiltier about this, because since the beginning of Zen they had only very seldom provided any information in advance about what features will be present in their next generation.
While there are many other policies that are very bad at Intel, at least they have remained the CPU company providing the best documentation for their products and they have always announced any ISA changes with at least one year, if not a few years, in advance. Therefore everybody has known about the proposed Intel Linear Address Masking, while nobody has known how AMD will do it.
The correction to the AMD address masking method is absolutely trivial, just disable the masking gate for the highest address bit, reducing the usable pointer tag from 7 bits to 6 bits, but maintaining compatibility with the existing operating systems.
This small change can be made in 5 minutes by the AMD CPU design team and it does not require any change in the existing mask layout.
At least one year has passed since Intel published their better version. Supposing that AMD has implemented their masking version in Zen 4, but they have kept this secret, I am pretty certain that 1 year ago AMD did not have their final mask set for Zen 4 and there have been some revisions since then. So there have certainly been opportunities when this could have been corrected without absolutely any cost for AMD.
It appears that nobody at AMD has realized that breaking software compatibility with their address masking variant is not good.
https://lore.kernel.org/lkml/20210205151631.43511-1-kirill.s...
BTW, MPX was clearly not the right thing. Nobody really wanted it. The world would be a better place if these address-bit-ignoring things (ARM TBI, AMD UAI, Intel LAM) had been implemented years ago instead all the effort spent on MPX.
Believe me, I know. I put a lot of blood, sweat and tears into MPX for Linux.
Disclaimer: If you didn't figure it out by now, I work on Linux at Intel.