So the "design limitation" in the chip can be overcome by updating apps to support Apple's TBDR tile memory system that was presumably created to maximize processor performance? Am I understanding the design limitation correctly?
TLB size is not where you're cutting costs. If you need to make it bigger so that common workloads can max out the other parts of the chip, it's a no-brainer decision. This isn't a sensible tradeoff.
What I'm confused with is how many silicon engineers are so easily able to make the absolute determination that "This isn't a sensible tradeoff."
The tweets terminology frankly seems weak, I've never even heard of a 32MB TLB - that's insanely huge.