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Comment by zamadatix | Hacker News Reader

x16+x4 has worked fine for consumers at PCIe 4.0 since GPUs aren't benefiting from the bandwidth so it should work fine with PCIe 5.0 and even if you bifurcate for x8 x8 + x4 so you can have another high speed addon card of some sort that's still ~250 Gbps of bandwidth per card which is more than any home or gaming setup will be bottlenecked by (workstation and server sure but those will be different boards).

I'm not quite sure the dual linked chipset option for the high end really gets anyone anything. I mean sure, double all your ports... where half now have 2x the latency penalty to the CPU and all in all they are sharing less bandwidth than your primary storage slot has alone.

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> where half now have 2x the latency penalty to the CPU

Are any of the typical uses for those IO lanes latency-sensitive enough for that to matter at all? Consumer-grade networking, SATA storage, and most USB use cases all involve latency high enough that one more PCIe switch wouldn't be noticed.

How much extra latency are we talking here? Anyone have any actual numbers?

I would guesstimate low single digit microseconds (and guesstimating latency is pretty much my job).

Typical USB poll rates are 10-100 milliseconds. AMD made a perfectly sensible choice.

Wat. All but the cheapest crappiest mice have been using 1ms polling for the last decade. IIRC USB 3.0 is effectively 8kHz and doesn’t use polling which does make a difference for real-time video (webcam and capture card) latency and lip syncing.

But nobody cares about USB. A lot of applications do 10000 reads from your SSD in series (qd1) and that’s where latency matters. I agree that it should be on the order of 1us. And since most people only have one SSD, chipset latency is not that important.

I would say what in a typical consumer setting even 2x latency for the NVMe drives wouldn't be noticeable, especially considering there is one directly on the CPU.

The NVMe off that second slot in particular is what's going to be painful for that market segment. If it weren't the topology that was only used specifically for the high performance market segment I'd say it doesn't matter but I'd be willing to bet most in that segment would actually want that 2nd x4 lane direct to the 1st chipset like last gen, not to the a second chipset just so they can have even more built in USB and SATA ports.

But who knows, maybe "I have a great gaming PC, it's got 25 USB ports!" (yes, that's the actual number) is more marketable than actually tuning for performance.

> The NVMe off that second slot in particular is what's going to be painful for that market segment.

Definitely not. Consumer Optane is dead, so the only devices that will get used in those slots have inherent latencies that are multiple orders of magnitude higher than those typical for a PCIe switch. The extra switch latency gets entirely lost in the noise, which I've observed on multiple occasions while reviewing "NVMe RAID" products.

It should be easily noticeable in benchmarks, after all a even 5% impact can still be called "multiple orders of magnitude" from being comparable to baseline. In double chain I'd be surprised if the impact was any less.

https://cdn.thefpsreview.com/wp-content/uploads/2021/09/crys...

Definitely not expecting end of the world numbers from it but at the same time I doubt many in the high end space are going to look at what that second chipset gives them and say "it's worth adding another PCIe switch in-between my addons for".

Of course you can just use the second x8 worth of bandwidth for drives but I'm not sure that sells having a chained chipset over just adding what you actually want to the first which would now have more open lanes anyways.

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