I have worked at an FPGA company, but on soft-IP, so I have some expertise but I wouldn't consider myself an expert, but I've certainly talked to them. What I observed is that whilst there technically is a bit pattern being programmed to hardware, the rules surrounding what combination of bits is incredibly complex. The simplest example of this is that you could programme two registers, one to drive a net low, the other to drive a net high and just basically screw up your chip. The rules that prevent that aren't a set of last minute "sign-off the image" type rules. Thhey're embedded into every part of the compiler. There were game changing hardware resources that genuinely were going to be hidden from customers because we didn't have the software resources to actually expose them in a safe manner (honestly, it's really very complex).

Ok, so that's the technical reasoning. On the business side, FPGA companies (like basically every ASIC company today) produce 1 design and disable a bunch of stuff for market segmentation. VU7P? Well that's physically the same as the VU5P but the software limits what you can compile on to it. So to enable open source interfaces they'd need to add an entire layer of DRM ontop of the current solutions. You can argue about the ethics, but it is what it is. Also, marketing drove Altera and Xilinx. Don't get any ideas that these were silicon valley engineer led start ups. It was a marketing game, you see that in their leadership and I'd argue you saw it in their share price growth too.

I really don't think the hardware specs is the issue. OSS EDA is miles behind commercial EDA. It's great that there are efforts to create an open ecosystem, and there are some chips that are usable in those flows, but the SW is orders of magnitude behind the proprietary tools.

I don't like that these proprietary tools are thrashed also, tools like Vivado are immensely complicated and surprisingly easy to use compared with other hardware tools. ASIC synthesis would make your cry compared with how easy Vivado makes it for FPGAs. Sure its not perfect, but it is free to use for many devices, and includes simulation, debug, SDKs, etc.

These companies are just twenty years behind the times. It’s why they lost the supercomputing market to NVidia. The FPGA vendors are also going to lose the DSP market to NVidia now, except for areas with extremely hard realtime requirements.

There are a whole lot of steps in between having a netlist and having useable hardware. Normally, if you're a large company, you have a small army of engineers handle that process and occasionally tell your architecture people that they need to fix up their designs here or there. When you target an FPGA, which is really more of an abstraction on top of silicon just like CPUs or GPUs are an abstraction on top of silicon, you're effectively paying them to do this process for you and mediate it via the software stack.

There's plenty to debate about where the boundary should be, but an almost universal constant is that ecosystems ossify around interfaces, so hardware companies will generally see giving up control as a borderline existential threat unless they're in the business of fishing pennies out of the gutter for margins.