I think of Ryzen as the first modern chip that has a multipurpose serdes, but here's PA Semi kicking out this [1] on their first & only chip:
> The device also integrates a flexible I/O subsystem that supports eight PCI Express controllers, two 10-Gigabit Ethernet controllers and four Gigabit Ethernet controllers that share 24 configurable SERDES lanes.
It's interesting that you highlight the cpu as such a limiting factor:
> they never publicly demonstrated any CPU that could actually drive all that bandwidth.
Agreed that the plans to scale up cores were very interesting & promising. But the other ultra-notable features of this ultra-integrated badass SoC monster (the one that shipped) was that it had a colossal crossbar powered DMA engine.
In many applications the cpu could serve as control plane, & the rest of the chip could act like a data-plane, shipping data around. The northbridge can happily pipe gobs of ethernet over to your SATA system, semi-autonomously.
At the time that usually took special carefully tuned code to pull off, I imagine. I like to think today we'd be able to use this DMA engine far more readily- io_uring for async io, all manners of dma-buf linux capabilities for managing device-side memory, plenty of dma engines & offloads in various kernel drivers. Direct device to device communication has continued to be underscores as a huge way to u leash computing, and wow, PA Semi dedicated gobs of die-space to the task way back then.
Such a huge huge pity such a promising new competitor just vanished.
> They had long-term plans, but they may have been starting to doubt the feasibility of executing them,
They indeed ran hotter than expected & core performance was not nearly what was hoped for. According to various LKML posts of people who had dev boxes. Still, so impressed. Tons of brilliant innovation. A little more runway to get off the ground before being torn apart & swallowed by a titan would have been great.
[1] http://vita.mil-embedded.com/news/p-processor-ever-designed/