This article really drives home the commonly ignored point about Intel CPUs: Sandy Bridge is a P4 derivative with all the faults fixed and the sharp edges filed off, not a P6/core 2 derivative.
That SB reintroduced netburst features doesn't change the history of the µarch. That's like saying Netburst not using a ROB means it was an evolution of Alpha rather than P6.
SB was not a renaissance of Netburst, it was a reintroduction, into the Core family, of features which Intel had first introduced in Netburst. Something which had already happened previously (e.g. hyperthreading in Nehalem) and would continue in the future (e. reintroduction of non-unified schedulers).
The "faults and sharp edges" of netburst were all caused by features which were at the core of netburst's identity, that's why it was a dead end and intel had to reset back to a sane working slate. As the article notes:
> Some of the fundamental ideas behind the architecture were definitely flawed.
And that Core was able to successfully integrate over time features first attempted in Netburst is exactly what you'd expect: many (though not all) of the individual features were not intrinsically bad and in fact several had been deployed successfully by other companies.
As the article specifically notes, the issues were introducing them all at once:
> Netburst debuted a mountain of new microarchitecture techniques. Some of these had been implemented by other companies, but were new to Intel. In general, the more you depart off the known path, the more risk you take. More changes mean more moving parts to tune and validate. Intel clearly took on way too much risk.
Especially in an architecture whose fundamental concepts and tradeoffs turned out to be unsound.
And you could say the same thing about Itanium. (In fact, Gordon Bell did.)
The real problem was Intel's focus on frequency above all else at the time. They were demoing I think a 10 GHz processor at Intel Developer Forum at one point.
A few years later as the world had pretty much entirely shifted to multicore, a senior Intel exec I was doing some work for basically told me that of course they knew the challenges around ramping frequency. But Microsoft was apparently very concerned about the ability of Windows to use multiple cores.
There was a lot of concern in the industry at the time around how well software--especially on the desktop--would be able to take advantage of multiple cores.
They knew they couldn’t keep it up. But when you have a process advantage you want to maintain it. To put it another way, they wouldn’t be sacrificing and advantage to make multi core chips.
This is why I think intel parts are so power hungry, this pathological focus on single core perf.
I don't know if they demoed that or not, but I can remember early claims in the press that they expected the P4/Netburst architecture to scale to 10GHz.
That's absolutely not how Sandy Bridge is designed. It's clearly a Core derivative with a uop cache, if you look at the overall structure of the pipeline. Yes, other ideas have been successfully integrated into Core derivatives such as SMT, better branch predictors and the Alpha-like OoO engine, but then even the first in-order Atoms had SMT.
Er, no. The structure of the pipeline is exactly what it took from the P4. P6 derivatives, including core, store in-flight results in the ROB, and then write them back to the RRF at retire. RRF read ports are a limited, shared resource, with full throughput only achieved when most instructions get their operands from the ROB.
P4 and SNB store only pointers in the ROB, putting all results directly into the PRF, with no work done on retire. The PRF has enough ports to serve all requests. This is an entirely different way to organize the cpu.
The structure of the Netburst front end depended heavily on the trace cache while the Sandy Bridge uop cache is more like an "L0" that can miss sometimes. The back end of Sandy Bridge doesn't need the messy replay system that was in Netburst. So this is what I meant by the pipeline being more similar to Nehalem.
For whatever reason, Intel called this mechanism “marbles”. There are a bunch of names in the industry for this: PRF, arch pointers, etc… its all the same thing.
By the way, moving to arch pointers is precisely what adds additional work on retirement: you need to do a walk or checkpoint restore to revert the arch state back to where it needs to be. With P6/Tomasulo, it is free. You got it backwards.