On the analog side you have a lot of custom transistors and hand drawn layout.
On the digital side it is Verilog RTL, synthesis to logic gates, and automated place and route.
The CAD flow is literally tens of thousands of lines of Tcl code gluing tools hundreds of libraries and tools from multiple vendors into something that just crashes once a day and not constantly.
There is still a lot of manual work involved even on the digital side. The number of PVT (Process / Voltage / Temperature) timing corners has exploded over the last decade. The design can have no logical bugs and timing closure still takes 6 months on big chips. Hundreds of clocks, new DRC violation types with every new process shrink. More tools to check IR drop, electromigration, yield enhancement.
One engineer is able to do something that would have taken 25 engineers 25 years ago but the chips have grown in size and complexity. We have over 50 physical design engineers on my current 20x20mm 5nm chip. Probably another 50 RTL designers, 10 DFT, an army of verification engineers. I'm ignoring the lab debug and software teams which I don't know as much about.
Designing with code is the only way to realistically do this on the schedules we have which are usually 1.5 to 2 years.