Are you seriously claiming that you expect a single node shrink from Intel 10nm (roughly equivalent to TSMC 7nm) to Intel 7nm (equivalent TSMC 5nm, the M1’s node) to give Intel an enormous 75% increase in IPC such that they’d be able to compete on performance per watt by not having to clock so stratospherically high (with the attendant voltage penalties) to compensate for their low IPC?
That would be an unprecedented outcome for several node shrinks, let alone a single one. It’s Apple’s super-wide design that’s the primary factor in the IPC here. To pin it all on a single node shrink is magical thinking.