20 wires for 112 options seems like a lot.
Shouldn't there be some way to just logic it down to something like 7?
Need to break out the karnaugh map.
Shouldn't there be some way to just logic it down to something like 7?
Need to break out the karnaugh map.
With your 112 key matrix, you can then use 14 input lines to make an 8x14 matrix, so you'd need a total of 17 GPIO pins.
You could also use 74251 8-to-1 multiplexer as that has an output enable, so you could use your remaining 2 outputs from the shift register to enable one of the two multiplexer chips. If you're not latching the outputs on the shift register, then you'd want a resistor between the two outputs so they don't fight.
So then, the ultimate reduction in GPIO would be to 3 lines - clock, data, in.
Obviously, for each of these, as you reduce the number of IO pins, you increase the time required to scan the matrix.
I have a current project where I needed to drive a large number of CS lines on a SPI bus. Others suggested I/O expanders and even - good lord - an entire M0 controller to handle it. I solved it with a bitbanged chain of 74HC595s, under $1 in BOM cost.