Well, now you know the answer is almost nobody :).

Xilinx and Altera have been promising efficient high level C++/openCL/CUDA -> FPGA compilation for decades now and almost everybody I know has been burnt by it at work, so thanks for confirming my bias, I'll avoid OneAPI too for the present. Guess VHDL and Verilog and the old standard tooling will live for another 10 years.

Everything is always amazing for the first 80% but the last 20% is impossible to fix and you end up not saving any dev time at all.