The only obvious downside I can see is that these protection limits have to be set
within the operational envelope of the CPU to be effective. That effectively narrows the range of possible voltages and frequencies that the user can use the CPU at. Some types of overclocking would go out of the window.
On the other hand, such checks could be disable-able at runtime by sufficiently trusted code - although you obviously have to choose between security and overclockability.
There is also the issue that such things are decidedly 'analogue' things - and integrating them into a digital design toolchain sounds hard. Trying to tell EDA software 'send this wire all the way around the outside of the chip and back to where it started' is a bit like trying to tell a C compiler 'I want you to write all the code so all jumps go to prime numbered memory addresses'.