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Comment by fulafel | Hacker News Reader

It seems there was a reboot in the AAarch64 (aka 64-bit ARM), and the general predication was jettisoned. Along with some other traditional ARM characteristic features like loading / storing multiple registers with one instruction.

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Loading and storing multiple registers is maybe most useful for loading a 64-bit value (e.g. double-precision floating-point) as two 32-bit pieces. Once you have direct 64-bit support it might be less useful?

LDP(load 2 registers) was switched in place of LDM, it seems that instructions that could touch so many registers at once made out of order/superscalar harder.

source: https://community.arm.com/support-forums/f/architectures-and...

Loading and storing multiple registers was mainly used in function prologues and epilogues, for saving and restoring the registers.

If you have to save e.g. 10 registers, using 40 bytes of instructions on function entry and another 40 bytes of instructions on function exit is a lot of wasted code space.

On Intel/AMD CPUs, the deprecation of the loading and storing of multiple registers (POPA and PUSHA) had less impact, because for pushing or popping a single register the length of an instruction is only 1 byte or 2 bytes, vs. 4 bytes on ARM.

To alleviate somewhat the removal of the instructions that could load and store up to all registers, in AArch64 double load and double store instructions have been added to the ISA, which can load or store a pair of distinct registers.

Loading/storing multiple registers was also more important for the early ARM processors, because they had no cache at all, so storing or loading registers one at a time required multiple instructions to be fetched from off-chip RAM, tying up bus bandwidth and stalling the pipeline (such as it was).

It's that it's a pain for precise exceptions. Handling how you get a page fault for ldm/stm and then restart them once the relevant page is loaded is non trivial.

Don't they still have to handle that for the remaining "load 2" instructions?

No, a single 128bit load/store even if it addresses two registers is way easier to handle than dumping a variable amount of your whole register file in a single instruction.

That's why the ARM1 had a microcode engine for LDM/STM despite having 'RISC' as the center letter in it's initialism.

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