Ask HN: Why are Intel E-Cores 1/4th the size of P-Cores | Hacker News Reader

Ask HN: Why are Intel E-Cores 1/4th the size of P-Cores

5 pointsKingOfCoders8 comments

I've searched the internet and all explainations pn E-Cores and P-Cores are shallow ones. Non explained why the E-Cores are so much smaller. Less cache? What functionality are they missing? AVX-512?

View on HN

Among other things, they do less per clock, which likely means fewer adders and other compute units, smaller storage to support a smaller amount of out of order operations, etc.

The E-Cores are an extension of the Atom cores, so you may be able to find older articles comparing their die size and structure to 'Core' cores. They've been about 1/3rd to 1/4th the size and around 1/2 the performance of similar age designs through most of their lifetime.

I would imagine the P-Cores have other dedicated circuitry for various features that the E-Cores lack. I believe the intent for this hetrogenous setup is to be akin to the big.LITTLE topology used in ARM systems.

Personally I'd like to see Linux/Windows perform when if scheduled to exclusively run on the E-Cores.

Any reduced functionality implies reduced area: the interesting question is choosing features given some area and power objective.

For example, fast (and hot) AVX-512 with a large area, slow AVX-512 with a reduced area, or no AVX-512: having the extension on the P-Cores only was deemed enough.

Less cache, much smaller OOO window, AVX-512. E-core is an area play so Intel can score some multi-thread benchmarketing wins on integer heavy code that don’t have larger memory/cache footprints, don’t require much speculative depth, and naturally have high amounts of ILP. They completely fall flat on plenty of workloads. And the way Intel runs them is absurd: 10+ watts per e-core just to eek out a MT win is pure absurdity.

Until Intel has a p-core that isn’t grossly obese, they have no option but to spam e-cores just to make powerpoint slides.

No AVX-512, less cache, lower frequency only one thread per core.

How does the lower frequency and one thread per core reduce the die size?

Lower frequency is less demanding, possibly allowing smaller or less numerous devices, more compact layouts for the same circuit, etc.

Less threads allows saving on elements that need to be faster to serve more threads, often with one instance per thread: for example, to run at full speed the instruction decoder needs to simultaneously decode one instruction per thread, and each thread is likely to need a separate set of registers to avoid the unpredictable delays and horrible complications of sharing them.

Thanks!

Reply on news.ycombinator.com