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Comment by PoignardAzur | Hacker News Reader

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PoignardAzur·

Summary:

- Prefetches predictable load patterns.

- Converts to micro-code.

- Does OoO execution.

- Renames registers to SSA-like form.

- Predicts branches.

(Man, seeing how much work the processor goes through to hammer x86 into something vaguely optimized, I really wish something like the Mill architecture had taken over so we'd get an instructions set made for compilers, not one that requires its own invisible compiler in the chip.)

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The downside of that approach is that the compiler doesn't have access to runtime information, or implementation details of the CPU (e.g. how many internal registers it has).

The solution to that is to have two stages of compilation: the first produces a binary with a general instruction set, and the second produces a binary with an instruction set specific to the machine it's installed on. (Though even with that approach you probably still need microcode)

The Mill architecture supposedly does this; the ISA has three variants for different product lines.

I think the point that was being made is that the _dynamic_ performance of the system is important too: branch prediction, cache access patterns etc, can't always be determined ahead of time, or even at the point the program is being installed or first run. This is why JIT compilers exist that tune the program as it runs, and this is what effectively is also happening at the micro-op level in your CPU as it runs.

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