Memristor cell scaled down to 10nm | Hacker News Reader

Memristor cell scaled down to 10nm

semiaccurate.com

46 pointsmrb11 comments

We already had MRAM which was non-volatile and was as fast as DRAM, but had horrible density. Now it looks like we have a workable device that can be both main memory and storage.

However, modern operating systems are all written with the assumption that your storage and memory are different things. Will these innovations see us going to the sort of system Multics tried to pioneer, with memory and storage unified in one filesytem?

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I the comment you're referring to on the article by "Christian" misread the stated numbers, specifically, it seems he ignored/misread the "in about 1ns" part, and then implies "1 billion reads/writes and switches total."

Article: > The cell has demonstrated an endurance of more than 1 billion reads/writes and switches in about 1ns.

Christian: > With a switching time of 1ns, you could do those 1 billion writes in 1 second flat.

What the the article is saying is that the device can endure more than 1 billion reads/writes and switches "within" 1ns. You could even say "per" 1ns if that reads better to you. What the device can endure within 1 full second is not stated, but may be extrapolated from the stated 1ns numbers.

No. Billion reads/writes within 1ns is simply not possible. That would imply that it can switch once per attosecond. Light cannot move more than 0.3nm, or one 30th of the length of this rram cell, in a single attosecond.

What the text means that it can switch once per 1ns, and it has proven to have endurance of more than billion switches for the lifetime of the cell. So yes, it can do all those billion in a single second. And yes, it thus probably isn't good enough to replace DRAM yet.

Actually, it would be possible. Under this speed, you would have an expressive delay (when compared to switching times) between the control and the output and the device would have parts of it in different states of a switch.

Not a very practical idea, but it's not impossible.

Actually, no. Memristors work by moving around oxygen atoms, and the read and write signals share wires. The write signal has to reach over the entire length of the cell, for some time, for a write to be successful. You can't even begin reading until the write has finished, and the write signal, which has orders of magnitude higher current than read, has been cleared from the wire.

Cool. I hadn't realized the read and write lines were the same. In that case, you really can't use the device as a delay-based sequential memory.

Thank you. I still think there is something unclear or incorrect in the article, or maybe I'm just more confused than usual. ;)

What is the common estimate as to how long it will be before we start seeing SSDs using these?

HP has announced something for 2013: http://www.eetimes.com/electronics-news/4229171/HP-Hynix-to-...

HP is still accumulating endurance cycle data at 10^12 cycles and the retention times are measured in years, he said. For all the people worried about the Semiaccurate article talking about only a billion read/write cycles, this shows that endurance is a very tuneable parameter, just like it is with flash memory. With flash you have some cells that are only good for 5K writes, and you have some that are good for 1M writes. With RRAM it looks like the numbers will be much higher.

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