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Comment by berkut | Hacker News Reader

Because the 'efficiency' cores are actually optimised for silicon area efficiency (and not just low power usage, like is generally the case with things like ARM big.LITTLE setups), and AVX-512 native takes up a lot of silicon space on the chips Intel has implemented it for.

And because it's not clear how OS schedulers could nicely switch on-the-fly between cores with different instruction set capabilities, it's essentially not use-able.

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> it's not clear how OS schedulers could nicely switch on-the-fly between cores with different instruction set capabilities

You would need a way for processes to signal the kernel that they have left a function that uses a higher instruction set and are thus available for moving to another core, plus a way for the kernel to signal processes to update their function pointers as appropriate for the new core they got moved to.

https://wiki.debian.org/InstructionSelection

> it's not clear how OS schedulers could nicely switch on-the-fly between cores with different instruction set capabilities

It is a software problem, and it could have been solved with software. It was simply assumed a priori that it couldn't be solved, so no one bothered to try.

Or they talked to Microsoft who said it would take years to add that feature.

Or they talked with Microsoft who refused to add it to anything but Windows 11. Or maybe they can't handle it because of some difficiency in their Linux ports.

The thing is it is possible and Intel knew for years that the E-cores wouldn't have AVX512.

Let it take years, then. Leaving it disabled in the bios by default is one thing, and a rather reasonable one at that. Fusing it off is quite another.

This isn't a new decision, it came out a few years ago that you'd end up with disparate instruction sets between the main and efficiency cores, and they got warned it would be a problem. Their disabling of the instructions to avoid it came about as a response. Both Microsoft and Linux devs warned them about the difficulties it'd present.

> And because it's not clear how OS schedulers could nicely switch on-the-fly between cores with different instruction set capabilities, it's essentially not use-able.

Couldn't you implement the new instructions (even slowly) in microcode? so they support the instructions with minimal silicon, even if its as slow or slower then other vector instructions?.

You generally can't add new huge ISA extensions like that in microcode without hardware support.

Ah yeah when I wrote that I forgot that AVX-512 brought in a tonne of new operations as well as larger register size..

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