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Let's spend multi-million dollars a year on a team of highly specialized FPGA engineers writing assembly and HDL so that we can save 5k a month. Feature velocity will be 100x slower as well, but at least our application is efficient.

I think that this may make sense for some applications, but I also think that if you can utilize software abstractions to improve developer efficiency, it reduces risk in the long run.

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Those millions of dollars have already been spent. For example the P4 [1] language (a HDL language) and the Tofino 3 chip. It started out as FPGA (NetFPGA) to do programmable packet routing at linespeed. You now have the P4 language to define your packet routers with and generate your code. Ten years later we have 25 Tbps software defined packet routers.

[1] https://en.wikipedia.org/wiki/P4_(programming_language)

[2] https://www.intel.com/content/www/us/en/products/network-io/...

>Let's spend multi-million dollars a year on a team of highly specialized FPGA engineers

I agree with you specialists are expensive but even a team of software engineers runs into the multi million dollar territory.

Why not spend the same amount AND cut down resource use? Hyperscalers have shifted to custom hardware already.

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